CHIP Simulation Results

Tuesday October 21 2025 17:24:04 UTC

GitHub Revision: `7c8100d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.927m	2.421ms	1	1	100.00
		chip_sw_example_rom	1.253m	2.231ms	1	1	100.00
		chip_sw_example_manufacturer	2.321m	2.697ms	1	1	100.00
		chip_sw_example_concurrency	2.310m	2.611ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.746m	6.175ms	1	1	100.00
V1	csr_rw	chip_csr_rw	6.970m	5.617ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	5.519m	6.044ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	51.965m	27.831ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	5.008m	6.643ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	51.965m	27.831ms	1	1	100.00
		chip_csr_rw	6.970m	5.617ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.340s	134.637us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.766m	3.418ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.766m	3.418ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.766m	3.418ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.673m	3.880ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.673m	3.880ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.065m	4.583ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.163m	4.191ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.244m	4.112ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	27.588m	12.937ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.847m	8.902ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	10.549m	8.315ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	3.012m	4.831ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.012m	4.831ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.649m	2.715ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.203m	3.103ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.999m	4.394ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	1.418m	2.162ms	1	1	100.00
		chip_tap_straps_testunlock0	12.038m	11.074ms	1	1	100.00
		chip_tap_straps_rma	4.550m	5.436ms	1	1	100.00
		chip_tap_straps_prod	1.405m	2.128ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.458m	3.047ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	14.679m	10.087ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.346m	5.098ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.346m	5.098ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.812m	8.397ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	25.151m	16.372ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.358m	4.451ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.284m	5.643ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.113m	19.145ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.964m	2.886ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	13.050m	7.337ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.067m	2.909ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.884m	10.066ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.841m	3.284ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.221m	3.439ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.025m	2.723ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.514m	3.217ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	5.393m	5.358ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.273m	5.113ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.231m	2.770ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.273m	5.113ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.818m	3.303ms	1	1	100.00
		chip_sw_aes_smoketest	2.149m	3.488ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.956m	2.910ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.699m	3.439ms	1	1	100.00
		chip_sw_csrng_smoketest	2.603m	2.232ms	1	1	100.00
		chip_sw_entropy_src_smoketest	10.480m	5.903ms	1	1	100.00
		chip_sw_gpio_smoketest	3.717m	3.438ms	1	1	100.00
		chip_sw_hmac_smoketest	3.405m	3.347ms	1	1	100.00
		chip_sw_kmac_smoketest	2.909m	2.924ms	1	1	100.00
		chip_sw_otbn_smoketest	8.498m	5.743ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.699m	6.247ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	3.154m	4.574ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.273m	2.845ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.655m	3.501ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.503m	2.917ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	2.198m	3.313ms	1	1	100.00
		chip_sw_uart_smoketest	2.054m	3.295ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.659m	2.970ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.048m	4.029ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.183h	61.618ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	43.319m	17.072ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.753m	5.853ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.108m	3.183ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	3.581m	3.206ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.873h	55.146ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.030h	56.922ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	52.880s	2.211ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	52.880s	2.211ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	51.965m	27.831ms	1	1	100.00
		chip_same_csr_outstanding	43.929m	30.310ms	1	1	100.00
		chip_csr_hw_reset	3.746m	6.175ms	1	1	100.00
		chip_csr_rw	6.970m	5.617ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	51.965m	27.831ms	1	1	100.00
		chip_same_csr_outstanding	43.929m	30.310ms	1	1	100.00
		chip_csr_hw_reset	3.746m	6.175ms	1	1	100.00
		chip_csr_rw	6.970m	5.617ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	12.860s	386.919us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	5.530s	44.767us	1	1	100.00
		xbar_smoke_large_delays	53.490s	8.339ms	1	1	100.00
		xbar_smoke_slow_rsp	50.940s	5.144ms	1	1	100.00
		xbar_random_zero_delays	15.690s	188.623us	1	1	100.00
		xbar_random_large_delays	4.568m	44.436ms	1	1	100.00
		xbar_random_slow_rsp	1.061m	7.112ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	22.960s	288.277us	1	1	100.00
		xbar_error_and_unmapped_addr	32.230s	1.261ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	56.120s	2.497ms	1	1	100.00
		xbar_error_and_unmapped_addr	32.230s	1.261ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.633m	3.940ms	1	1	100.00
		xbar_access_same_device_slow_rsp	2.533m	16.258ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	31.930s	1.591ms	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	54.840s	2.916ms	1	1	100.00
		xbar_stress_all_with_error	43.310s	2.141ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	11.406m	26.660ms	1	1	100.00
		xbar_stress_all_with_reset_error	2.174m	5.556ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	43.319m	17.072ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	19.443m	22.523ms	0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	41.732m	15.240ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	33.205m	11.138ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	44.201m	18.386ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	43.251m	15.534ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	40.597m	15.238ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	39.972m	16.551ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	16.660s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	21.820s	10.140us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	21.190s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	20.250s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	25.580s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	22.650s	10.280us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	23.130s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	21.530s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	25.700s	10.300us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	16.670s	10.240us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.230s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	19.920s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	20.630s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	20.510s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.270s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	21.780s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	18.800s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	17.250s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	18.970s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.990s	10.240us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	19.030s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.330s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.930s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.810s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.110s	10.340us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	31.748m	11.802ms	1	1	100.00
		rom_e2e_asm_init_dev	40.123m	15.550ms	1	1	100.00
		rom_e2e_asm_init_prod	41.040m	15.747ms	1	1	100.00
		rom_e2e_asm_init_prod_end	41.595m	15.843ms	1	1	100.00
		rom_e2e_asm_init_rma	38.797m	15.271ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	39.568m	16.460ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	38.556m	15.498ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	38.822m	15.749ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	39.870m	15.905ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.844m	34.134ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.844m	34.134ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.576m	2.436ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.964m	2.886ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.966m	2.328ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.497m	2.976ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	17.174m	8.595ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.435m	3.046ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	6.053m	6.240ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.712m	5.053ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	8.442m	5.564ms	1	1	100.00
		chip_plic_all_irqs_10	4.273m	3.098ms	1	1	100.00
		chip_plic_all_irqs_20	6.184m	4.815ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.288m	3.318ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	17.696m	11.107ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.837m	3.366ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.425m	2.398ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	16.696m	7.111ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	16.915m	8.121ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	14.502m	7.519ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.066h	254.916ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.170m	3.518ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.699m	6.247ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.170m	3.518ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.607m	7.283ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.607m	7.283ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.909m	6.861ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	5.357m	6.122ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.674m	6.223ms	1	1	100.00
		chip_sw_aes_idle	2.497m	2.976ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.397m	3.086ms	1	1	100.00
		chip_sw_kmac_idle	1.689m	2.381ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.298m	4.724ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.844m	3.851ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	4.023m	4.170ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.089m	3.459ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	14.181m	10.843ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.109m	3.639ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.723m	4.187ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.769m	3.597ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.096m	5.012ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.511m	4.371ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.390m	4.668ms	1	1	100.00
		chip_sw_ast_clk_outputs	10.812m	8.397ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.919m	6.617ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.769m	3.597ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.096m	5.012ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.358m	4.451ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.284m	5.643ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.113m	19.145ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.964m	2.886ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	13.050m	7.337ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.067m	2.909ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.884m	10.066ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.841m	3.284ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.221m	3.439ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.025m	2.723ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.872m	2.778ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.474m	4.283ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	11.027m	6.813ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	49.918m	24.206ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	3.099m	3.415ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.236m	2.982ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	12.221m	9.343ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.879m	3.084ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.119m	3.737ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	20.648m	24.574ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.070h	141.807ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.812m	8.397ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.001m	4.277ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.765m	3.755ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.712m	5.053ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	16.696m	7.111ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	19.863m	8.522ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	4.471m	4.693ms	1	1	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.833m	7.395ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.880m	2.597ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	30.378m	11.229ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.795m	2.767ms	1	1	100.00
		chip_sw_edn_entropy_reqs	10.436m	5.390ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.795m	2.767ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	19.863m	8.522ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.633m	2.619ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.585m	23.108ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	9.252m	5.363ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.284m	5.643ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.132m	3.794ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.358m	4.451ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	56.087m	44.035ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.585m	23.108ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.207m	3.749ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	11.717m	7.233ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.822m	5.009ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	56.087m	44.035ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.822m	5.009ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.822m	5.009ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.822m	5.009ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.822m	5.009ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.712m	5.053ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.774m	8.828ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.394m	5.398ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.418m	4.607ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.418m	4.607ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.664m	2.590ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	3.067m	2.909ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.397m	3.086ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.633m	2.772ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.668m	3.625ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.755m	4.343ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.309m	4.729ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	6.348m	4.557ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.168m	3.795ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	11.717m	7.233ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.884m	10.066ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	10.828m	7.427ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	17.174m	8.595ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	38.279m	11.659ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.151m	3.229ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.807m	3.714ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.841m	3.284ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	11.717m	7.233ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.185m	6.984ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.778m	2.346ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	9.312m	5.501ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	1.689m	2.381ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	6.053m	6.240ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	1.418m	2.162ms	1	1	100.00
		chip_tap_straps_rma	4.550m	5.436ms	1	1	100.00
		chip_tap_straps_prod	1.405m	2.128ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.112m	3.101ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.185m	6.984ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.185m	6.984ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.185m	6.984ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	15.531m	7.807ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.822m	5.009ms	1	1	100.00
		chip_sw_flash_rma_unlocked	56.087m	44.035ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.810m	3.302ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.933m	6.482ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.726m	5.973ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.255m	6.692ms	0	1	0.00
		chip_sw_lc_ctrl_transition	5.185m	6.984ms	1	1	100.00
		chip_sw_keymgr_key_derivation	11.717m	7.233ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.561m	8.411ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.539m	8.593ms	1	1	100.00
		chip_prim_tl_access	3.774m	8.828ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.919m	6.617ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.109m	3.639ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.723m	4.187ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.769m	3.597ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	6.096m	5.012ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.511m	4.371ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.390m	4.668ms	1	1	100.00
		chip_tap_straps_dev	1.418m	2.162ms	1	1	100.00
		chip_tap_straps_rma	4.550m	5.436ms	1	1	100.00
		chip_tap_straps_prod	1.405m	2.128ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.470m	10.343ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.207m	3.375ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.278m	3.704ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.798m	3.100ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	32.230m	27.187ms	0	1	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	22.127m	27.646ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.470m	10.343ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.069h	51.120ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.063h	46.411ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.927m	8.477ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.133h	46.334ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	22.127m	27.646ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.032m	2.275ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.000m	2.417ms	1	1	100.00
		rom_volatile_raw_unlock	1.082m	1.941ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	55.352m	17.122ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.113m	19.145ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.674m	6.223ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.674m	6.223ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.674m	6.223ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.606m	3.648ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.185m	6.984ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.585m	23.108ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.606m	3.648ms	1	1	100.00
		chip_sw_keymgr_key_derivation	11.717m	7.233ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.659m	5.194ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.068m	2.665ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.585m	23.108ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.606m	3.648ms	1	1	100.00
		chip_sw_keymgr_key_derivation	11.717m	7.233ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	5.659m	5.194ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.068m	2.665ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.185m	6.984ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	6.215m	4.070ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	3.112m	3.101ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.810m	3.302ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.933m	6.482ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	7.726m	5.973ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	7.255m	6.692ms	0	1	0.00
		chip_sw_lc_ctrl_transition	5.185m	6.984ms	1	1	100.00
		chip_prim_tl_access	3.774m	8.828ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.774m	8.828ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	19.501m	8.780ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	6.540m	8.024ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	20.568m	27.798ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	3.785m	7.732ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	7.604m	10.314ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	6.687m	5.695ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	17.269m	23.724ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	12.434m	14.870ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.607m	7.283ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.206m	13.194ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.859m	5.223ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	6.540m	8.024ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.718m	3.396ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	28.618m	38.282ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.473m	5.976ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.170m	6.067ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.830m	22.701ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.338m	7.496ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	16.166m	9.850ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	23.466m	27.981ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.589m	2.438ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.712m	5.053ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.561m	8.411ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.561m	8.411ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	16.166m	9.850ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.830m	22.701ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.859m	5.223ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.699m	6.247ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.137m	3.655ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.090m	3.366ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.279m	3.460ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	17.696m	11.107ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.788m	3.680ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.712m	5.053ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	16.915m	8.121ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.357m	4.879ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.767m	5.274ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.666m	3.616ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.068m	2.665ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.090m	3.366ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.090m	3.366ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	10.031m	9.212ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	16.077m	13.763ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.137m	3.655ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	3.749m	4.173ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	3.366m	5.800ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	4.550m	5.436ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.470m	10.343ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	8.442m	5.564ms	1	1	100.00
		chip_plic_all_irqs_10	4.273m	3.098ms	1	1	100.00
		chip_plic_all_irqs_20	6.184m	4.815ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.661m	3.269ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.874m	2.761ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	43.319m	17.072ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.900m	6.602ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	2.781m	3.079ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.599m	3.455ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	3.331m	3.151ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	5.659m	5.194ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.221m	3.439ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.899m	7.793ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	5.883m	8.135ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.539m	8.593ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.712m	5.053ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.346m	5.098ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	11.338m	7.496ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	16.224m	21.814ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.341m	2.759ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.768m	3.794ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.660m	4.091ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	16.224m	21.814ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	16.224m	21.814ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	38.202m	20.605ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	38.202m	20.605ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.972m	6.293ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	48.844m	34.134ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.478m	3.307ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.375m	3.331ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	3.906m	3.223ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.503m	3.850ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.170m	7.599ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.363h	31.369ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.433m	11.956ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.258m	2.878ms	1	1	100.00
V2		TOTAL			235	275	85.45
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.447m	3.053ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.828m	2.742ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.632h	72.278ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	17.407m	6.509ms	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	20.061m	12.013ms	1	1	100.00
		rom_e2e_jtag_debug_dev	2.958m	4.382ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.680m	12.473ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.953m	4.608ms	1	1	100.00
		rom_e2e_jtag_inject_dev	4.651m	5.009ms	1	1	100.00
		rom_e2e_jtag_inject_rma	2.441m	4.084ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	13.816s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.950m	5.578ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.207m	2.903ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	18.386m	6.866ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	18.064m	8.419ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.700m	2.555ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.607m	5.209ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.263m	2.281ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	5.757m	4.331ms	1	1	100.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	4.154m	6.389ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	6.005m	5.804ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	16.166m	9.850ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	20.061m	12.013ms	1	1	100.00
		rom_e2e_jtag_debug_dev	2.958m	4.382ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.680m	12.473ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.350m	4.899ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.712m	5.053ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.469h	38.476ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.469h	38.476ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.857m	3.572ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.673m	3.880ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	53.864m	19.097ms	1	1	100.00
V3		TOTAL			21	23	91.30
	Unmapped tests	chip_sival_flash_info_access	2.605m	3.175ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.049m	4.425ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	40.269m	25.793ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.769m	2.433ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.666m	3.152ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.278m	3.945ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	14.291s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.297m	2.828ms	1	1	100.00
		TOTAL			282	326	86.50

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.87686112577148466014803712865789284970270542225138507138066933856770878370235
    Line 485, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.77293276937286106972481591778897401875348302561182848635640203637622712317190
    Line 487, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.67095885960617427843117844164917306559668973142211099519561943049238809241
    Line 476, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.99264850560511693956373072121959575930234220572224052710082451088787323369280
    Line 486, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.39916419651871568760618948287566307817574960747227839675301207092457737381720
    Line 527, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.46706158170122922850787696079012195963906947634279488456548362781688398307758
    Line 473, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.31946060175282357940724705619906837853138169189725670629303803722784343480514
    Line 477, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.102984346889367379396582596406515937670443483901353864263866373643949325690369
    Line 485, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.50416149996866365188103235630040158239477621865196865156845840440486996694277
    Line 491, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.103699919317481029740704944247103632577255911021674451629963409184862382797191
    Line 482, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.62598148167452084698835725154682680940731560320308760882479351339221974325514
    Line 466, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.40912482539178308840680166277207897884669822936424258947960884108727895308808
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.18767594934788433254450619419652987299613166476953559681561949071439359536285
    Line 481, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.85972403417706981404642472591313164896148605137693831139179952983073892976981
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 1.011s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.37898770916824347018666518798698707949858264203940162611542717865238016530751
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.574s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.76014913364293164353527133672996684458087125813105834554653141213622878245304
    Line 544, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.25300908905784354379850541032637424973480742424548002069979080383758319665561
    Line 554, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.36242175173394415564245026390402485282828107500903971311326638846213180657359
    Line 592, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.76470763914534147255194737381873905976461061029414919643349162637811938749377
    Line 538, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.38953232939659639645471462679655411536853755003579290179463670757554694464138
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3078.912271 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
  host_rsp:
  -------------------------------------------------------------------------
  Name                               Type              Size  Value
  -------------------------------------------------------------------------
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.40276275003464925315966588531792392455204463989086491139965538683840549847168
    Line 424, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6692.361296 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6692.361296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.48382115061588937787308500097479047911619586010720810269204369572195982681279
    Line 434, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 25792.765635 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 25792.765635 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:827) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! has 1 failures:
- Test chip_sw_lc_ctrl_rand_to_scrap has 1 failures.
  - 0.chip_sw_lc_ctrl_rand_to_scrap.105936300849423572311788376857854457155829696088154454415697547490597808592670
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_rand_to_scrap/latest/run.log
```
  UVM_FATAL @ 27187.070126 us: (chip_sw_base_vseq.sv:827) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!
  UVM_INFO @ 27187.070126 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78434) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.17067060119947143133598477549699052441099851645385718026790470687735049012440
Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 3366.220200 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@78434) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3366.220200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.71748417307258853862648027110931973720095098898235300849949149033443127885178
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34133.610154 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34133.610154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.88474669874420462474592991501192781593947309768188384286734527331730774330964
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3046.204781 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 3046.204781 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.91422933811625315742978919670868548701390163590579699355906172902583319084775
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2398.495840 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2398.495840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.39304394347001205151288962749778302137509065853945280284940477127410662819548
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.55921474887080920518321532513144536526128463334386564085939789964503642789226
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2772.121785 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2772.121785 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33842) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.98294541709225490483013928720997387179791005513045528682024510674418176007541
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2210.735668 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33842) { a_addr: 'h10364  a_data: 'haace7a88  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc  a_opcode: 'h4  a_user: 'h1b62f  d_param: 'h0  d_source: 'hc  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2210.735668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.113826103498621226862729014581572734590757921025445475801264380337294543711206
    Line 239, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 10342.660355 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10510 read out mismatch
  UVM_INFO @ 10342.660355 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.74131456635019804172110941661663717748125074251030322854017842372802472779149
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3182.780000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3182.780000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.62379583610148675844899653196660777637546427134464489163385517266230600113621
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3205.935000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3205.935000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.47262631672888424899100049290079503495470637816581353884823708559340117645884
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 16371.933769 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 16371.933769 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rom_e2e_shutdown_output_vseq.sv:23) [chip_sw_rom_e2e_shutdown_output_vseq] wait timeout occurred! has 1 failures:
- Test rom_e2e_shutdown_output has 1 failures.
  - 0.rom_e2e_shutdown_output.10907728774053395754938313856536783928120521348780832177008934346023837456651
    Line 464, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_shutdown_output/latest/run.log
```
  UVM_FATAL @ 22522.551045 us: (chip_sw_rom_e2e_shutdown_output_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] wait timeout occurred!
  UVM_INFO @ 22522.551045 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.111268546102032874919926876743855672083053367689234182322652144659220172810380
    Line 479, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.82941452774138438894606035886209243724160332772671969778188271632949149525495
    Line 433, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.107485147276539463036416275534784338552737111687833235942526775608618198746477
    Line 442, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 4381.907350 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 4381.907350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```