ADC_CTRL Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	13.120s	5.774ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	2.180s	663.044us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.660s	359.302us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.632m	26.903ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.090s	1.560ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.180s	533.075us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.660s	359.302us	1	1	100.00
		adc_ctrl_csr_aliasing	2.090s	1.560ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	13.658m	494.827ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	1.077m	168.865ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	10.855m	486.370ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	5.134m	322.815ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	1.084m	399.260ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.514m	207.166ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	7.217m	519.160ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	4.683m	166.358ms	1	1	100.00
V2	poweron_counter	adc_ctrl_poweron_counter	0.950s	3.070ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	11.730s	40.157ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	1.852m	123.170ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	8.917m	307.004ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.310s	326.550us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.500s	409.158us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.360s	561.059us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.360s	561.059us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	2.180s	663.044us	1	1	100.00
		adc_ctrl_csr_rw	1.660s	359.302us	1	1	100.00
		adc_ctrl_csr_aliasing	2.090s	1.560ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.920s	2.338ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	2.180s	663.044us	1	1	100.00
		adc_ctrl_csr_rw	1.660s	359.302us	1	1	100.00
		adc_ctrl_csr_aliasing	2.090s	1.560ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	5.920s	2.338ms	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	tl_intg_err	adc_ctrl_sec_cm	4.060s	4.392ms	1	1	100.00
		adc_ctrl_tl_intg_err	2.390s	4.935ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	2.390s	4.935ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	3.680s	1.477ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	25	100.00