EDN Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 0.870s 31.299us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.840s 25.054us 1 1 100.00
V1 csr_rw edn_csr_rw 0.770s 102.262us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.320s 516.969us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.080s 34.509us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 0.930s 193.645us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.770s 102.262us 1 1 100.00
edn_csr_aliasing 1.080s 34.509us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.050s 56.504us 1 1 100.00
V2 csrng_commands edn_genbits 1.050s 56.504us 1 1 100.00
V2 genbits edn_genbits 1.050s 56.504us 1 1 100.00
V2 interrupts edn_intr 1.010s 24.326us 1 1 100.00
V2 alerts edn_alert 1.040s 94.084us 1 1 100.00
V2 errs edn_err 0.900s 58.336us 1 1 100.00
V2 disable edn_disable 0.720s 59.326us 1 1 100.00
edn_disable_auto_req_mode 0.950s 97.279us 1 1 100.00
V2 stress_all edn_stress_all 2.680s 167.453us 1 1 100.00
V2 intr_test edn_intr_test 0.710s 27.785us 1 1 100.00
V2 alert_test edn_alert_test 0.790s 14.741us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 2.060s 282.364us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 2.060s 282.364us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.840s 25.054us 1 1 100.00
edn_csr_rw 0.770s 102.262us 1 1 100.00
edn_csr_aliasing 1.080s 34.509us 1 1 100.00
edn_same_csr_outstanding 0.880s 31.608us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.840s 25.054us 1 1 100.00
edn_csr_rw 0.770s 102.262us 1 1 100.00
edn_csr_aliasing 1.080s 34.509us 1 1 100.00
edn_same_csr_outstanding 0.880s 31.608us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 4.770s 406.920us 1 1 100.00
edn_tl_intg_err 1.290s 96.912us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 0.860s 40.186us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.040s 94.084us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 4.770s 406.920us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 4.770s 406.920us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 4.770s 406.920us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 4.770s 406.920us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.040s 94.084us 1 1 100.00
edn_sec_cm 4.770s 406.920us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.040s 94.084us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 1.290s 96.912us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets