HMAC Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.340s 60.993us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.880s 57.468us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.980s 24.863us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.760s 460.616us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.720s 649.994us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.450s 37.340us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.980s 24.863us 1 1 100.00
hmac_csr_aliasing 5.720s 649.994us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 14.730s 18.419ms 1 1 100.00
V2 back_pressure hmac_back_pressure 53.220s 19.172ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.240s 389.533us 1 1 100.00
hmac_test_sha384_vectors 19.060s 271.024us 1 1 100.00
hmac_test_sha512_vectors 17.910s 234.527us 1 1 100.00
hmac_test_hmac256_vectors 5.320s 732.361us 1 1 100.00
hmac_test_hmac384_vectors 8.870s 1.350ms 1 1 100.00
hmac_test_hmac512_vectors 5.590s 168.764us 1 1 100.00
V2 burst_wr hmac_burst_wr 11.840s 332.705us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 7.904m 18.526ms 1 1 100.00
V2 error hmac_error 1.140s 52.859us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.459m 38.851ms 1 1 100.00
V2 save_and_restore hmac_smoke 2.340s 60.993us 1 1 100.00
hmac_long_msg 14.730s 18.419ms 1 1 100.00
hmac_back_pressure 53.220s 19.172ms 1 1 100.00
hmac_datapath_stress 7.904m 18.526ms 1 1 100.00
hmac_burst_wr 11.840s 332.705us 1 1 100.00
hmac_stress_all 18.312m 9.019ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.340s 60.993us 1 1 100.00
hmac_long_msg 14.730s 18.419ms 1 1 100.00
hmac_back_pressure 53.220s 19.172ms 1 1 100.00
hmac_datapath_stress 7.904m 18.526ms 1 1 100.00
hmac_wipe_secret 1.459m 38.851ms 1 1 100.00
hmac_test_sha256_vectors 8.240s 389.533us 1 1 100.00
hmac_test_sha384_vectors 19.060s 271.024us 1 1 100.00
hmac_test_sha512_vectors 17.910s 234.527us 1 1 100.00
hmac_test_hmac256_vectors 5.320s 732.361us 1 1 100.00
hmac_test_hmac384_vectors 8.870s 1.350ms 1 1 100.00
hmac_test_hmac512_vectors 5.590s 168.764us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.340s 60.993us 1 1 100.00
hmac_long_msg 14.730s 18.419ms 1 1 100.00
hmac_back_pressure 53.220s 19.172ms 1 1 100.00
hmac_datapath_stress 7.904m 18.526ms 1 1 100.00
hmac_burst_wr 11.840s 332.705us 1 1 100.00
hmac_error 1.140s 52.859us 1 1 100.00
hmac_wipe_secret 1.459m 38.851ms 1 1 100.00
hmac_test_sha256_vectors 8.240s 389.533us 1 1 100.00
hmac_test_sha384_vectors 19.060s 271.024us 1 1 100.00
hmac_test_sha512_vectors 17.910s 234.527us 1 1 100.00
hmac_test_hmac256_vectors 5.320s 732.361us 1 1 100.00
hmac_test_hmac384_vectors 8.870s 1.350ms 1 1 100.00
hmac_test_hmac512_vectors 5.590s 168.764us 1 1 100.00
hmac_stress_all 18.312m 9.019ms 1 1 100.00
V2 stress_all hmac_stress_all 18.312m 9.019ms 1 1 100.00
V2 alert_test hmac_alert_test 0.670s 71.100us 1 1 100.00
V2 intr_test hmac_intr_test 0.790s 58.295us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.200s 250.416us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.200s 250.416us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.880s 57.468us 1 1 100.00
hmac_csr_rw 0.980s 24.863us 1 1 100.00
hmac_csr_aliasing 5.720s 649.994us 1 1 100.00
hmac_same_csr_outstanding 1.720s 385.773us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.880s 57.468us 1 1 100.00
hmac_csr_rw 0.980s 24.863us 1 1 100.00
hmac_csr_aliasing 5.720s 649.994us 1 1 100.00
hmac_same_csr_outstanding 1.720s 385.773us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.030s 239.146us 1 1 100.00
hmac_tl_intg_err 2.380s 600.035us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.380s 600.035us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.340s 60.993us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.270s 48.403us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 10.027m 111.772ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.240s 89.385us 1 1 100.00
TOTAL 28 28 100.00