I2C Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	52.980s	1.699ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	23.090s	1.057ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.770s	40.482us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.690s	44.986us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	1.910s	157.351us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.680s	218.032us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.780s	75.451us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.690s	44.986us	1	1	100.00
		i2c_csr_aliasing	1.680s	218.032us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.860s	304.797us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	22.128m	85.189ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	5.766m	29.106ms	1	1	100.00
V2	host_override	i2c_host_override	0.690s	19.394us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	54.910s	4.168ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.450m	2.059ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.840s	101.938us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.900s	2.163ms	1	1	100.00
		i2c_host_fifo_reset_rx	4.340s	219.350us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	40.860s	3.560ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	27.340s	3.141ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.800s	23.832us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.530s	1.743ms	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.995m	42.060ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.600s	1.080ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	16.210s	2.124ms	1	1	100.00
		i2c_target_intr_smoke	3.760s	1.381ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.640s	196.238us	1	1	100.00
		i2c_target_fifo_reset_tx	1.730s	231.089us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	8.040s	23.324ms	1	1	100.00
		i2c_target_stress_rd	16.210s	2.124ms	1	1	100.00
		i2c_target_intr_stress_wr	3.908m	19.740ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.970s	1.041ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	1.910s	596.615us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.030s	2.859ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	3.050s	11.574ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.450s	1.015ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.130s	133.679us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	5.766m	29.106ms	1	1	100.00
		i2c_host_perf_precise	32.690s	2.868ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	27.340s	3.141ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.890s	288.035us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.530s	740.364us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.020s	1.751ms	1	1	100.00
		i2c_target_nack_txstretch	1.440s	634.965us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.120s	1.298ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.060s	6.469ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.610s	66.131us	1	1	100.00
V2	intr_test	i2c_intr_test	0.670s	30.605us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.080s	27.593us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.080s	27.593us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.770s	40.482us	1	1	100.00
		i2c_csr_rw	0.690s	44.986us	1	1	100.00
		i2c_csr_aliasing	1.680s	218.032us	1	1	100.00
		i2c_same_csr_outstanding	0.930s	32.297us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.770s	40.482us	1	1	100.00
		i2c_csr_rw	0.690s	44.986us	1	1	100.00
		i2c_csr_aliasing	1.680s	218.032us	1	1	100.00
		i2c_same_csr_outstanding	0.930s	32.297us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	1.210s	336.654us	1	1	100.00
		i2c_sec_cm	0.810s	44.251us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.210s	336.654us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	31.320s	1.768ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.170s	40.282us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	27.340s	3.811ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.67108440956378434930773985313070366238486523004656265895856867945888278991057
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @ 304796650 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 304796650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.60370530251688245092354547488163443833048966631070520803382819339216405480633
      Line 104, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3810729047 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 3810729047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.40992164333423316366568112693090900626488539010370255971072255588868065307748
      Line 78, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  23831684 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  23831684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.55109308739490119335189527963136579946863787988781074040718479118315077078081
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 1742735354 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 1742735354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.100473347557403374254157343989397197229585565536999850355144508267763147245493
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  40281619 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 208 [0xd0])
        UVM_INFO @  40281619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.5073194527376024173373799239687207948580265996456966123175880719639876986078
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 11573508173 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 11573508173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.101129977811124017603528847206142435742995368425880017290028196322622254850449
      Line 109, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1768479915 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1768479915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---