KMAC/UNMASKED Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	7.780s	221.208us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	119.625us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.930s	60.088us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.850s	1.960ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.280s	305.086us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.870s	77.796us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.930s	60.088us	1	1	100.00
		kmac_csr_aliasing	3.280s	305.086us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.860s	58.599us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.410s	36.608us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	22.872m	19.849ms	1	1	100.00
V2	burst_write	kmac_burst_write	12.410m	52.040ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.293m	122.830ms	1	1	100.00
		kmac_test_vectors_sha3_256	18.969m	82.291ms	1	1	100.00
		kmac_test_vectors_sha3_384	14.666m	27.493ms	1	1	100.00
		kmac_test_vectors_sha3_512	11.513m	30.783ms	1	1	100.00
		kmac_test_vectors_shake_128	2.679m	44.377ms	1	1	100.00
		kmac_test_vectors_shake_256	4.469m	44.863ms	1	1	100.00
		kmac_test_vectors_kmac	1.950s	33.495us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.200s	485.011us	1	1	100.00
V2	sideload	kmac_sideload	57.360s	8.028ms	1	1	100.00
V2	app	kmac_app	1.180m	21.988ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.812m	27.520ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.821m	9.070ms	1	1	100.00
V2	error	kmac_error	2.738m	7.705ms	1	1	100.00
V2	key_error	kmac_key_error	9.250s	1.275ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.180s	133.557us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	23.440s	1.193ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	3.610s	146.857us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	39.230s	11.592ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.100s	103.372us	1	1	100.00
V2	stress_all	kmac_stress_all	9.429m	57.159ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.750s	16.526us	1	1	100.00
V2	alert_test	kmac_alert_test	1.110s	19.504us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.650s	56.381us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.650s	56.381us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	119.625us	1	1	100.00
		kmac_csr_rw	0.930s	60.088us	1	1	100.00
		kmac_csr_aliasing	3.280s	305.086us	1	1	100.00
		kmac_same_csr_outstanding	1.860s	68.827us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	119.625us	1	1	100.00
		kmac_csr_rw	0.930s	60.088us	1	1	100.00
		kmac_csr_aliasing	3.280s	305.086us	1	1	100.00
		kmac_same_csr_outstanding	1.860s	68.827us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.110s	315.446us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.110s	315.446us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.110s	315.446us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.110s	315.446us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.440s	228.760us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	59.270s	22.753ms	1	1	100.00
		kmac_tl_intg_err	1.860s	98.367us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.860s	98.367us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.100s	103.372us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	7.780s	221.208us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	57.360s	8.028ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.110s	315.446us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	59.270s	22.753ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	59.270s	22.753ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	59.270s	22.753ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	7.780s	221.208us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.100s	103.372us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	59.270s	22.753ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.154m	74.760ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	7.780s	221.208us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.180s	2.730ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.98732118405414523052187736692476728182565675972991939744534808763855609925760
      Line 133, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2730477433 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2730477433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---