PATTGEN Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: `fc2d73b`

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	33.667us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	12.600us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	24.759us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	284.044us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	58.561us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	2.000s	170.775us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	24.759us	1	1	100.00
		pattgen_csr_aliasing	2.000s	58.561us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	14.583m	600.000ms	0	1	0.00
V2	cnt_rollover	cnt_rollover	16.000s	4.980ms	1	1	100.00
V2	error	pattgen_error	7.000s	79.518us	1	1	100.00
V2	stress_all	pattgen_stress_all	9.067m	93.195ms	0	1	0.00
V2	alert_test	pattgen_alert_test	2.000s	15.052us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	13.526us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	474.957us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	474.957us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	12.600us	1	1	100.00
		pattgen_csr_rw	1.000s	24.759us	1	1	100.00
		pattgen_csr_aliasing	2.000s	58.561us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	27.367us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	12.600us	1	1	100.00
		pattgen_csr_rw	1.000s	24.759us	1	1	100.00
		pattgen_csr_aliasing	2.000s	58.561us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	27.367us	1	1	100.00
V2		TOTAL			6	8	75.00
V2S	tl_intg_err	pattgen_tl_intg_err	2.000s	254.636us	1	1	100.00
		pattgen_sec_cm	3.000s	94.128us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000s	254.636us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	55.000s	13.340ms	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	7.000s	63.769us	1	1	100.00
		TOTAL			15	18	83.33

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pattgen_perf has 1 failures.
  - 0.pattgen_perf.60993672938903499713848785690946462659119386368919934166170562197499200137575
    Line 96, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_perf/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test pattgen_stress_all_with_rand_reset has 1 failures.

0.pattgen_stress_all_with_rand_reset.80353307234290764474102664621125537192214113249880487597305270733194181113548
Line 258, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9048878157 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 9048903567 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9048903567 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/10
  UVM_INFO @ 9049278570 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all has 1 failures.
  - 0.pattgen_stress_all.46192975586068511638524513159378430790185383090257011288682258540811750905911
    Line 150, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 93194683496 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10266
```