ROM_CTRL/32KB Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 6.820s 1.259ms 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.990s 420.872us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.080s 372.441us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.210s 173.011us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.900s 819.458us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.840s 141.945us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.080s 372.441us 1 1 100.00
rom_ctrl_csr_aliasing 5.900s 819.458us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.840s 129.505us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.600s 172.238us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.410s 139.410us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 20.330s 12.529ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 7.520s 1.077ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 3.530s 500.100us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.110s 165.466us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.110s 165.466us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.990s 420.872us 1 1 100.00
rom_ctrl_csr_rw 4.080s 372.441us 1 1 100.00
rom_ctrl_csr_aliasing 5.900s 819.458us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.900s 627.009us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.990s 420.872us 1 1 100.00
rom_ctrl_csr_rw 4.080s 372.441us 1 1 100.00
rom_ctrl_csr_aliasing 5.900s 819.458us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.900s 627.009us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.358m 15.105ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 15.350s 587.158us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 3.397m 666.405us 1 1 100.00
rom_ctrl_tl_intg_err 27.240s 251.661us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 3.397m 666.405us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 3.397m 666.405us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.358m 15.105ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.358m 15.105ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.358m 15.105ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.358m 15.105ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.358m 15.105ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 3.397m 666.405us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 3.397m 666.405us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 6.820s 1.259ms 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 6.820s 1.259ms 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 6.820s 1.259ms 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 27.240s 251.661us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.358m 15.105ms 1 1 100.00
rom_ctrl_kmac_err_chk 7.520s 1.077ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.358m 15.105ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.358m 15.105ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.358m 15.105ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 15.350s 587.158us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 3.397m 666.405us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.811m 10.030ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00