RV_DM/USE_JTAG_INTERFACE Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: `fc2d73b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	3.540s	3.799ms	1	1	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.010s	112.679us	1	1	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.050s	152.882us	1	1	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	2.770s	8.551ms	1	1	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	0.870s	266.770us	1	1	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	15.810s	15.577ms	1	1	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	4.280s	4.751ms	1	1	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	2.505m	83.425ms	1	1	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	1.594m	214.168ms	1	1	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	0.860s	767.918us	1	1	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.110s	765.248us	1	1	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.210s	1.016ms	1	1	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.140s	381.378us	1	1	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	0.730s	262.991us	1	1	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.170s	574.810us	1	1	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.800s	209.356us	1	1	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	3.350s	1.450ms	1	1	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	0.860s	767.918us	1	1	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.720s	117.294us	1	1	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.330s	343.128us	1	1	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.210s	1.016ms	1	1	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.960s	134.555us	1	1	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	1.880s	249.897us	1	1	100.00
V1	csr_rw	rv_dm_csr_rw	1.260s	427.432us	1	1	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	18.190s	3.523ms	1	1	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	43.720s	1.137ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	1.530s	147.259us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	43.720s	1.137ms	1	1	100.00
		rv_dm_csr_rw	1.260s	427.432us	1	1	100.00
V1	mem_walk	rv_dm_mem_walk	0.780s	69.395us	1	1	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.780s	150.637us	1	1	100.00
V1		TOTAL			27	27	100.00
V2	idcode	rv_dm_smoke	3.540s	3.799ms	1	1	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	0.840s	216.378us	1	1	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.050s	328.837us	1	1	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.840s	189.561us	1	1	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.640s	1.065ms	1	1	100.00
V2	sba	rv_dm_sba_tl_access	9.954m	300.000ms	0	1	0.00
		rv_dm_delayed_resp_sba_tl_access	8.978m	300.000ms	0	1	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	8.577m	300.000ms	0	1	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	3.569m	300.000ms	0	1	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	0.700s	119.515us	1	1	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	1.160s	654.783us	1	1	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	0.970s	232.129us	1	1	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.200s	364.639us	1	1	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	7.130s	13.165ms	0	1	0.00
		rv_dm_tap_fsm_rand_reset	1.410s	61.875us	0	1	0.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.860s	64.317us	1	1	100.00
V2	stress_all	rv_dm_stress_all	3.290s	1.397ms	1	1	100.00
V2	alert_test	rv_dm_alert_test	0.730s	104.475us	1	1	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	1.050s	87.403us	0	1	0.00
V2	tl_d_illegal_access	rv_dm_tl_errors	1.050s	87.403us	0	1	0.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	43.720s	1.137ms	1	1	100.00
		rv_dm_csr_hw_reset	1.880s	249.897us	1	1	100.00
		rv_dm_csr_rw	1.260s	427.432us	1	1	100.00
		rv_dm_same_csr_outstanding	2.940s	228.054us	1	1	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	43.720s	1.137ms	1	1	100.00
		rv_dm_csr_hw_reset	1.880s	249.897us	1	1	100.00
		rv_dm_csr_rw	1.260s	427.432us	1	1	100.00
		rv_dm_same_csr_outstanding	2.940s	228.054us	1	1	100.00
V2		TOTAL			12	19	63.16
V2S	tl_intg_err	rv_dm_sec_cm	2.050s	2.504ms	1	1	100.00
		rv_dm_tl_intg_err	14.720s	2.764ms	1	1	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	14.720s	2.764ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	1.160s	654.783us	1	1	100.00
		rv_dm_debug_disabled	1.040s	102.776us	1	1	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	1.160s	654.783us	1	1	100.00
		rv_dm_debug_disabled	1.040s	102.776us	1	1	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	3.540s	3.799ms	1	1	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	1.230s	324.355us	1	1	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.790s	156.931us	1	1	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.790s	156.931us	1	1	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	1.230s	324.355us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.900s	413.202us	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	rv_dm_scanmode	0.710s	14.180us	1	1	100.00
		TOTAL			45	53	84.91

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test rv_dm_sba_tl_access has 1 failures.
  - 0.rv_dm_sba_tl_access.31398600938071048778566821381769738688844543863556739297477608448007471560315
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
  - 0.rv_dm_delayed_resp_sba_tl_access.67036972755300192789786889950309791806442239407037767150896668353359601036680
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_bad_sba_tl_access has 1 failures.
  - 0.rv_dm_bad_sba_tl_access.27528481579776921999545982508109244476753686484872840387739384599011467741678
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_autoincr_sba_tl_access has 1 failures.
  - 0.rv_dm_autoincr_sba_tl_access.15798004353781118558483828248186451934103607818925307333673809838382745152152
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[NOA] Null object access has 1 failures:
- Test rv_dm_tap_fsm has 1 failures.
  - 0.rv_dm_tap_fsm.47134754865753643673451856595530045375000139934808370027326180950023302894841
    Line 108, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
```
  Error-[NOA] Null object access
  src/lowrisc_dv_cip_lib_0/seq_lib/cip_base_vseq.sv, 638
    The object at dereference depth 0 is being used before it was
    constructed/allocated.
    Please make sure that the object is allocated before using it.
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@17992) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_tap_fsm_rand_reset has 1 failures.

0.rv_dm_tap_fsm_rand_reset.77345274954978273881481876518689514298654198984510797816983689663631643683182
Line 82, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @  61875449 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@17992) { a_addr: 'h83c726bc  a_data: 'h81260638  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h49  a_opcode: 'h4  a_user: 'h193be  d_param: 'h0  d_source: 'h49  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  61875449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@40632) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_stress_all_with_rand_reset has 1 failures.

0.rv_dm_stress_all_with_rand_reset.28022030193539029202951868425659008263716824033796347767706416180567297353973
Line 79, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 413202077 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@40632) { a_addr: 'h8f154340  a_data: 'hc460d13c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'heb  a_opcode: 'h4  a_user: 'h18892  d_param: 'h0  d_source: 'heb  d_data: 'hc55513  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd33  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 413202077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6190) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_tl_errors has 1 failures.

0.rv_dm_tl_errors.62376630142401063757915545240943406789883900272508707287152775572251529390591
Line 75, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tl_errors/latest/run.log

  UVM_ERROR @  87403319 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@6190) { a_addr: 'h3b391660  a_data: 'h4de5d91  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h4  a_user: 'h199f2  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  87403319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---