RV_TIMER Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.220s	1.318ms	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.680s	16.545us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.680s	23.565us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.180s	106.350us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.840s	29.729us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.760s	104.593us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.680s	23.565us	1	1	100.00
		rv_timer_csr_aliasing	0.840s	29.729us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.750s	85.910us	0	1	0.00
V2	disabled	rv_timer_disabled	1.790s	3.111ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	9.785m	442.456ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	9.785m	442.456ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.150s	7.091ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.630s	14.305us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.580s	30.270us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.070s	83.303us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.070s	83.303us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.680s	16.545us	1	1	100.00
		rv_timer_csr_rw	0.680s	23.565us	1	1	100.00
		rv_timer_csr_aliasing	0.840s	29.729us	1	1	100.00
		rv_timer_same_csr_outstanding	0.650s	259.444us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.680s	16.545us	1	1	100.00
		rv_timer_csr_rw	0.680s	23.565us	1	1	100.00
		rv_timer_csr_aliasing	0.840s	29.729us	1	1	100.00
		rv_timer_same_csr_outstanding	0.650s	259.444us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.940s	194.478us	1	1	100.00
		rv_timer_tl_intg_err	0.980s	51.287us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	0.980s	51.287us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.910s	128.176us	0	1	0.00
V3	max_value	rv_timer_max	0.840s	46.528us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	4.460s	2.173ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			15	19	78.95

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.45649598989997341031523460130077323902441105632533125484640287856165664901474
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 128176362 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x771d5b04) == 0x1
        UVM_INFO @ 128176362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.50242354247720206497052832558031610219191390717035802587363094061615323726137
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @  85909901 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x1685b704) == 0x1
        UVM_INFO @  85909901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.4335054004613415281107884428555660217611517372197088038392835289671179712460
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  46527599 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  46527599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (cip_base_vseq.sv:1163) [rv_timer_common_vseq] Check failed (vseq_done) has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.23792115998221083818203639079237102373710115891362321764514583078088779851999
      Line 184, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 2172967275 ps: (cip_base_vseq.sv:1163) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done)
        UVM_INFO @ 2172967275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---