SPI_DEVICE/1R1W Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	33.490s	16.957ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.330s	25.638us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.540s	70.006us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.420s	2.423ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	11.340s	609.370us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.070s	358.017us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.540s	70.006us	1	1	100.00
		spi_device_csr_aliasing	11.340s	609.370us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	93.813us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	0.990s	56.722us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.900s	60.901us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.800s	14.629us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	3.955us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.190s	52.423us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.190s	52.423us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	8.290s	36.328ms	1	1	100.00
		spi_device_tpm_sts_read	0.770s	77.382us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	27.520s	8.132ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.510s	4.956ms	1	1	100.00
		spi_device_flash_all	3.602m	52.343ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.690s	3.625ms	1	1	100.00
		spi_device_flash_all	3.602m	52.343ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.690s	3.625ms	1	1	100.00
		spi_device_flash_all	3.602m	52.343ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	3.602m	52.343ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	19.790s	5.448ms	1	1	100.00
		spi_device_flash_all	3.602m	52.343ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	19.790s	5.448ms	1	1	100.00
		spi_device_flash_all	3.602m	52.343ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	19.790s	5.448ms	1	1	100.00
		spi_device_flash_all	3.602m	52.343ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	19.790s	5.448ms	1	1	100.00
		spi_device_flash_all	3.602m	52.343ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	19.790s	5.448ms	1	1	100.00
		spi_device_flash_all	3.602m	52.343ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	18.430s	86.120ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	9.540s	4.898ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	9.540s	4.898ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	9.540s	4.898ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.630s	853.285us	1	1	100.00
		spi_device_read_buffer_direct	4.340s	963.374us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	9.540s	4.898ms	1	1	100.00
		spi_device_flash_all	3.602m	52.343ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	3.602m	52.343ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	3.602m	52.343ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.170s	281.179us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.170s	281.179us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	33.490s	16.957ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.760m	71.735ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.227m	26.676ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.700s	40.948us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.820s	15.743us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.770s	154.793us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.770s	154.793us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.330s	25.638us	1	1	100.00
		spi_device_csr_rw	1.540s	70.006us	1	1	100.00
		spi_device_csr_aliasing	11.340s	609.370us	1	1	100.00
		spi_device_same_csr_outstanding	2.420s	114.969us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.330s	25.638us	1	1	100.00
		spi_device_csr_rw	1.540s	70.006us	1	1	100.00
		spi_device_csr_aliasing	11.340s	609.370us	1	1	100.00
		spi_device_same_csr_outstanding	2.420s	114.969us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.230s	340.312us	1	1	100.00
		spi_device_tl_intg_err	8.040s	697.357us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	8.040s	697.357us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.384m	20.097ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.1720949384020081111909431324742177656055730827665468851824213503940938408258
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   9073474 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[0])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   9073474 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   9073474 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[896])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.4249404168361035475525741833916606516260591838674582824887741688089055548524
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1459437 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4b7f80 [10010110111111110000000] vs 0x0 [0])
        UVM_ERROR @   1480437 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5539bf [10101010011100110111111] vs 0x0 [0])
        UVM_ERROR @   1484437 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x722cda [11100100010110011011010] vs 0x0 [0])
        UVM_ERROR @   1576437 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1dc082 [111011100000010000010] vs 0x0 [0])
        UVM_ERROR @   1589437 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1cb45 [11100101101000101] vs 0x0 [0])