SPI_DEVICE/2P Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke spi_device_flash_and_tpm 43.050s 13.489ms 1 1 100.00
V1 csr_hw_reset spi_device_csr_hw_reset 1.160s 134.941us 1 1 100.00
V1 csr_rw spi_device_csr_rw 1.160s 39.498us 1 1 100.00
V1 csr_bit_bash spi_device_csr_bit_bash 9.880s 947.752us 1 1 100.00
V1 csr_aliasing spi_device_csr_aliasing 5.310s 535.534us 1 1 100.00
V1 csr_mem_rw_with_rand_reset spi_device_csr_mem_rw_with_rand_reset 3.060s 986.528us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr spi_device_csr_rw 1.160s 39.498us 1 1 100.00
spi_device_csr_aliasing 5.310s 535.534us 1 1 100.00
V1 mem_walk spi_device_mem_walk 0.770s 18.926us 1 1 100.00
V1 mem_partial_access spi_device_mem_partial_access 1.470s 49.014us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 csb_read spi_device_csb_read 0.810s 16.207us 1 1 100.00
V2 mem_parity spi_device_mem_parity 1.060s 98.259us 1 1 100.00
V2 mem_cfg spi_device_ram_cfg 0.730s 55.535us 1 1 100.00
V2 tpm_read spi_device_tpm_rw 1.140s 20.168us 1 1 100.00
V2 tpm_write spi_device_tpm_rw 1.140s 20.168us 1 1 100.00
V2 tpm_hw_reg spi_device_tpm_read_hw_reg 5.340s 6.175ms 1 1 100.00
spi_device_tpm_sts_read 0.830s 96.949us 1 1 100.00
V2 tpm_fully_random_case spi_device_tpm_all 15.470s 2.361ms 1 1 100.00
V2 pass_cmd_filtering spi_device_pass_cmd_filtering 4.380s 19.606ms 1 1 100.00
spi_device_flash_all 0.740s 33.083us 1 1 100.00
V2 pass_addr_translation spi_device_pass_addr_payload_swap 7.760s 9.109ms 1 1 100.00
spi_device_flash_all 0.740s 33.083us 1 1 100.00
V2 pass_payload_translation spi_device_pass_addr_payload_swap 7.760s 9.109ms 1 1 100.00
spi_device_flash_all 0.740s 33.083us 1 1 100.00
V2 cmd_info_slots spi_device_flash_all 0.740s 33.083us 1 1 100.00
V2 cmd_read_status spi_device_intercept 3.130s 214.958us 1 1 100.00
spi_device_flash_all 0.740s 33.083us 1 1 100.00
V2 cmd_read_jedec spi_device_intercept 3.130s 214.958us 1 1 100.00
spi_device_flash_all 0.740s 33.083us 1 1 100.00
V2 cmd_read_sfdp spi_device_intercept 3.130s 214.958us 1 1 100.00
spi_device_flash_all 0.740s 33.083us 1 1 100.00
V2 cmd_fast_read spi_device_intercept 3.130s 214.958us 1 1 100.00
spi_device_flash_all 0.740s 33.083us 1 1 100.00
V2 cmd_read_pipeline spi_device_intercept 3.130s 214.958us 1 1 100.00
spi_device_flash_all 0.740s 33.083us 1 1 100.00
V2 flash_cmd_upload spi_device_upload 2.250s 815.426us 1 1 100.00
V2 mailbox_command spi_device_mailbox 6.170s 1.278ms 1 1 100.00
V2 mailbox_cross_outside_command spi_device_mailbox 6.170s 1.278ms 1 1 100.00
V2 mailbox_cross_inside_command spi_device_mailbox 6.170s 1.278ms 1 1 100.00
V2 cmd_read_buffer spi_device_flash_mode 26.140s 12.964ms 1 1 100.00
spi_device_read_buffer_direct 9.410s 1.320ms 1 1 100.00
V2 cmd_dummy_cycle spi_device_mailbox 6.170s 1.278ms 1 1 100.00
spi_device_flash_all 0.740s 33.083us 1 1 100.00
V2 quad_spi spi_device_flash_all 0.740s 33.083us 1 1 100.00
V2 dual_spi spi_device_flash_all 0.740s 33.083us 1 1 100.00
V2 4b_3b_feature spi_device_cfg_cmd 5.370s 2.250ms 1 1 100.00
V2 write_enable_disable spi_device_cfg_cmd 5.370s 2.250ms 1 1 100.00
V2 TPM_with_flash_or_passthrough_mode spi_device_flash_and_tpm 43.050s 13.489ms 1 1 100.00
V2 tpm_and_flash_trans_with_min_inactive_time spi_device_flash_and_tpm_min_idle 3.803m 82.808ms 1 1 100.00
V2 stress_all spi_device_stress_all 6.720s 6.158ms 1 1 100.00
V2 alert_test spi_device_alert_test 0.790s 59.851us 1 1 100.00
V2 intr_test spi_device_intr_test 0.700s 78.754us 1 1 100.00
V2 tl_d_oob_addr_access spi_device_tl_errors 3.490s 771.354us 1 1 100.00
V2 tl_d_illegal_access spi_device_tl_errors 3.490s 771.354us 1 1 100.00
V2 tl_d_outstanding_access spi_device_csr_hw_reset 1.160s 134.941us 1 1 100.00
spi_device_csr_rw 1.160s 39.498us 1 1 100.00
spi_device_csr_aliasing 5.310s 535.534us 1 1 100.00
spi_device_same_csr_outstanding 1.770s 375.865us 1 1 100.00
V2 tl_d_partial_access spi_device_csr_hw_reset 1.160s 134.941us 1 1 100.00
spi_device_csr_rw 1.160s 39.498us 1 1 100.00
spi_device_csr_aliasing 5.310s 535.534us 1 1 100.00
spi_device_same_csr_outstanding 1.770s 375.865us 1 1 100.00
V2 TOTAL 22 22 100.00
V2S tl_intg_err spi_device_sec_cm 1.000s 79.153us 1 1 100.00
spi_device_tl_intg_err 5.140s 225.466us 1 1 100.00
V2S sec_cm_bus_integrity spi_device_tl_intg_err 5.140s 225.466us 1 1 100.00
V2S TOTAL 2 2 100.00
Unmapped tests spi_device_flash_mode_ignore_cmds 27.640s 2.171ms 1 1 100.00
TOTAL 33 33 100.00