SPI_HOST Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	3.000s	183.727us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	46.490us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	18.415us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	68.231us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	32.845us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	1.000s	77.156us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	18.415us	1	1	100.00
		spi_host_csr_aliasing	2.000s	32.845us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	17.778us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	56.961us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	34.826us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	6.000s	868.360us	1	1	100.00
		spi_host_error_cmd	1.000s	19.060us	1	1	100.00
		spi_host_event	9.000s	920.073us	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	59.683us	1	1	100.00
V2	speed	spi_host_speed	3.000s	59.683us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	59.683us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	4.000s	213.391us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	28.021us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	59.683us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	59.683us	1	1	100.00
V2	duplex	spi_host_smoke	3.000s	183.727us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	3.000s	183.727us	1	1	100.00
V2	stress_all	spi_host_stress_all	11.000s	655.330us	1	1	100.00
V2	spien	spi_host_spien	9.000s	1.008ms	1	1	100.00
V2	stall	spi_host_status_stall	1.333m	15.656ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	195.217us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	6.000s	868.360us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	17.151us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	53.315us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	53.510us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	53.510us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	46.490us	1	1	100.00
		spi_host_csr_rw	1.000s	18.415us	1	1	100.00
		spi_host_csr_aliasing	2.000s	32.845us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	28.240us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	46.490us	1	1	100.00
		spi_host_csr_rw	1.000s	18.415us	1	1	100.00
		spi_host_csr_aliasing	2.000s	32.845us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	28.240us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	1.000s	119.841us	1	1	100.00
		spi_host_sec_cm	1.000s	130.838us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.000s	119.841us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	3.933m	14.612ms	1	1	100.00
		TOTAL			26	26	100.00