SRAM_CTRL/MAIN Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.080m	3.458ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.980s	23.480us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.000s	44.816us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.910s	48.420us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.830s	99.948us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	5.450s	466.968us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.000s	44.816us	1	1	100.00
		sram_ctrl_csr_aliasing	0.830s	99.948us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.108m	57.606ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.139m	5.526ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.562m	2.106ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.890m	6.713ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	17.154m	153.819ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.901m	23.021ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	38.260s	17.755ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.417m	21.073ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.880s	758.661us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.102m	8.047ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	5.730s	3.321ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	5.260s	670.929us	1	1	100.00
		sram_ctrl_throughput_w_readback	15.770s	982.660us	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.103m	24.731ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.580s	719.506us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	25.958m	162.057ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.950s	32.854us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.700s	140.076us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.700s	140.076us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.980s	23.480us	1	1	100.00
		sram_ctrl_csr_rw	1.000s	44.816us	1	1	100.00
		sram_ctrl_csr_aliasing	0.830s	99.948us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.920s	30.134us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.980s	23.480us	1	1	100.00
		sram_ctrl_csr_rw	1.000s	44.816us	1	1	100.00
		sram_ctrl_csr_aliasing	0.830s	99.948us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.920s	30.134us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	21.950s	3.817ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.890s	5.157us	0	1	0.00
		sram_ctrl_tl_intg_err	2.170s	184.266us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.890s	5.157us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.170s	184.266us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.103m	24.731ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.103m	24.731ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.000s	44.816us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.417m	21.073ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.417m	21.073ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.417m	21.073ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	38.260s	17.755ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.770s	2.655ms	0	1	0.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	21.950s	3.817ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.950s	2.751ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.080m	3.458ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.080m	3.458ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.417m	21.073ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.890s	5.157us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	38.260s	17.755ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.890s	5.157us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.890s	5.157us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.080m	3.458ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.890s	5.157us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	13.590s	508.841us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• Offending 'reqfifo_rvalid' has 1 failures:

  • Test sram_ctrl_mubi_enc_err has 1 failures.

    • 0.sram_ctrl_mubi_enc_err.96437086266719687476041045492616386957320602291998480828111198434464058980251
      Line 101, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2655021889 ps: (tlul_adapter_sram.sv:636) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2655021889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.9879466883052748695777616925763311532088739129225640974687746331801067005497
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   5157386 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   5157386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---