SRAM_CTRL/RET Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.730s	2.367ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.640s	15.978us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.700s	27.281us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.510s	87.620us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.800s	19.006us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.010s	98.518us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.700s	27.281us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	19.006us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.710s	110.759us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.670s	2.706ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	3.319m	30.018ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.475m	2.121ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	40.660s	952.033us	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.218m	2.947ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	3.160s	418.314us	1	1	100.00
V2	executable	sram_ctrl_executable	7.009m	10.034ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	27.780s	206.417us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.718m	47.043ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	29.710s	295.237us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	25.510s	126.548us	1	1	100.00
		sram_ctrl_throughput_w_readback	4.220s	96.041us	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.511m	9.510ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.700s	29.872us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	25.680m	22.492ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.730s	14.069us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.010s	242.783us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.010s	242.783us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.640s	15.978us	1	1	100.00
		sram_ctrl_csr_rw	0.700s	27.281us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	19.006us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	40.155us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.640s	15.978us	1	1	100.00
		sram_ctrl_csr_rw	0.700s	27.281us	1	1	100.00
		sram_ctrl_csr_aliasing	0.800s	19.006us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	40.155us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.510s	792.664us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.860s	6.778us	0	1	0.00
		sram_ctrl_tl_intg_err	1.440s	245.394us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.860s	6.778us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.440s	245.394us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.511m	9.510ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.511m	9.510ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.700s	27.281us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.009m	10.034ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.009m	10.034ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.009m	10.034ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	3.160s	418.314us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.840s	40.424us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.510s	792.664us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.840s	90.120us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.730s	2.367ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.730s	2.367ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.009m	10.034ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.860s	6.778us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	3.160s	418.314us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.860s	6.778us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.860s	6.778us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.730s	2.367ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.860s	6.778us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.870m	27.911ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.109350846692297411272345263795247227870053607516734039262587466838763119544121
      Line 102, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6777918 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6777918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---