SYSRST_CTRL Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 1.590s 2.125ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 1.070s 2.499ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 3.130s 2.408ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.860s 2.332ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 11.300s 6.035ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 4.260s 2.059ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 2.120m 39.054ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 2.910s 2.706ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 2.300s 2.180ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 4.260s 2.059ms 1 1 100.00
sysrst_ctrl_csr_aliasing 2.910s 2.706ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 1.352m 158.363ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 4.406m 148.644ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 3.540s 3.921ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 1.870s 3.150ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 3.140s 2.519ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 4.650s 2.125ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 6.450s 3.116ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 6.100s 2.608ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 29.650s 255.142ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 15.660s 37.698ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 12.900s 6.861ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 1.230s 2.059ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 1.150s 2.075ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.290s 2.517ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.290s 2.517ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 11.300s 6.035ms 1 1 100.00
sysrst_ctrl_csr_rw 4.260s 2.059ms 1 1 100.00
sysrst_ctrl_csr_aliasing 2.910s 2.706ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 25.580s 10.285ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 11.300s 6.035ms 1 1 100.00
sysrst_ctrl_csr_rw 4.260s 2.059ms 1 1 100.00
sysrst_ctrl_csr_aliasing 2.910s 2.706ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 25.580s 10.285ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 1.383m 42.015ms 1 1 100.00
sysrst_ctrl_tl_intg_err 1.260m 42.497ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.260m 42.497ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 5.690s 2.615ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00