UART Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	11.530s	5.550ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.600s	61.037us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.620s	41.722us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.230s	557.661us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.770s	32.279us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.810s	58.132us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.620s	41.722us	1	1	100.00
		uart_csr_aliasing	0.770s	32.279us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	13.340s	22.596ms	1	1	100.00
V2	parity	uart_smoke	11.530s	5.550ms	1	1	100.00
		uart_tx_rx	13.340s	22.596ms	1	1	100.00
V2	parity_error	uart_intr	38.350s	31.980ms	1	1	100.00
		uart_rx_parity_err	26.920s	110.662ms	1	1	100.00
V2	watermark	uart_tx_rx	13.340s	22.596ms	1	1	100.00
		uart_intr	38.350s	31.980ms	1	1	100.00
V2	fifo_full	uart_fifo_full	9.190s	14.099ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	6.340s	9.259ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.421m	88.013ms	1	1	100.00
V2	rx_frame_err	uart_intr	38.350s	31.980ms	1	1	100.00
V2	rx_break_err	uart_intr	38.350s	31.980ms	1	1	100.00
V2	rx_timeout	uart_intr	38.350s	31.980ms	1	1	100.00
V2	perf	uart_perf	13.706m	26.977ms	1	1	100.00
V2	sys_loopback	uart_loopback	7.340s	12.472ms	1	1	100.00
V2	line_loopback	uart_loopback	7.340s	12.472ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	5.280s	4.040ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.910s	4.712ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	5.930s	1.239ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	10.400s	5.442ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	11.299m	97.155ms	1	1	100.00
V2	stress_all	uart_stress_all	4.763m	308.019ms	1	1	100.00
V2	alert_test	uart_alert_test	0.660s	123.922us	1	1	100.00
V2	intr_test	uart_intr_test	0.680s	32.925us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.030s	83.672us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.030s	83.672us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.600s	61.037us	1	1	100.00
		uart_csr_rw	0.620s	41.722us	1	1	100.00
		uart_csr_aliasing	0.770s	32.279us	1	1	100.00
		uart_same_csr_outstanding	0.810s	87.497us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.600s	61.037us	1	1	100.00
		uart_csr_rw	0.620s	41.722us	1	1	100.00
		uart_csr_aliasing	0.770s	32.279us	1	1	100.00
		uart_same_csr_outstanding	0.810s	87.497us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.080s	352.915us	1	1	100.00
		uart_tl_intg_err	1.330s	94.604us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.330s	94.604us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	17.250s	11.494ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.26257699518538455305984311686556631624211309527464239925907329268539206716445
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 3976678255 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3978625565 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3987814763 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3992540937 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 3992656723 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0