CHIP Simulation Results

Wednesday October 22 2025 17:25:38 UTC

GitHub Revision: `fc2d73b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.008m	2.975ms	1	1	100.00
		chip_sw_example_rom	1.232m	2.822ms	1	1	100.00
		chip_sw_example_manufacturer	2.684m	3.331ms	1	1	100.00
		chip_sw_example_concurrency	3.160m	3.529ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.522m	6.886ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.292m	4.517ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	3.738m	4.469ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	58.863m	30.258ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	55.300s	2.173ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	58.863m	30.258ms	1	1	100.00
		chip_csr_rw	3.292m	4.517ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.370s	229.207us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.248m	3.735ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.248m	3.735ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.248m	3.735ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.148m	4.195ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.148m	4.195ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.681m	4.149ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.148m	4.284ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.874m	4.512ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	6.678m	4.646ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	16.260m	7.875ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	18.478m	13.360ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	3.093m	4.762ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.093m	4.762ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.714m	2.973ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.139m	5.404ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.372m	3.366ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	15.834m	15.553ms	1	1	100.00
		chip_tap_straps_testunlock0	4.832m	5.038ms	1	1	100.00
		chip_tap_straps_rma	1.476m	2.233ms	1	1	100.00
		chip_tap_straps_prod	17.562m	15.034ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.310m	3.119ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.916m	8.645ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.824m	6.185ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.824m	6.185ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.082m	7.501ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	44.306m	23.045ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.271m	4.785ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	11.037m	6.467ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.849m	18.882ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.592m	2.345ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.130m	5.094ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.691m	2.939ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.732m	9.281ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.402m	3.081ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.321m	4.055ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.996m	2.834ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.834m	2.446ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	9.329m	7.381ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.140m	5.775ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.913m	2.132ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.140m	5.775ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	1.804m	2.636ms	1	1	100.00
		chip_sw_aes_smoketest	2.399m	2.628ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.139m	3.500ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.783m	2.455ms	1	1	100.00
		chip_sw_csrng_smoketest	2.061m	2.216ms	1	1	100.00
		chip_sw_entropy_src_smoketest	16.759m	8.199ms	1	1	100.00
		chip_sw_gpio_smoketest	2.559m	2.869ms	1	1	100.00
		chip_sw_hmac_smoketest	3.389m	3.239ms	1	1	100.00
		chip_sw_kmac_smoketest	3.062m	3.120ms	1	1	100.00
		chip_sw_otbn_smoketest	23.314m	11.299ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.728m	5.716ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.001m	6.142ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.342m	2.399ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.868m	2.951ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.477m	3.006ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.830m	2.705ms	1	1	100.00
		chip_sw_uart_smoketest	2.515m	3.320ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.325m	2.594ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	5.135m	4.226ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.082h	60.622ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	42.433m	14.846ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.203m	4.848ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	2.679m	3.345ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.938m	3.176ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.920h	54.177ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.989h	57.426ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.342m	3.495ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.342m	3.495ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	58.863m	30.258ms	1	1	100.00
		chip_same_csr_outstanding	20.910m	16.018ms	1	1	100.00
		chip_csr_hw_reset	3.522m	6.886ms	1	1	100.00
		chip_csr_rw	3.292m	4.517ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	58.863m	30.258ms	1	1	100.00
		chip_same_csr_outstanding	20.910m	16.018ms	1	1	100.00
		chip_csr_hw_reset	3.522m	6.886ms	1	1	100.00
		chip_csr_rw	3.292m	4.517ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	13.950s	215.396us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	6.430s	48.369us	1	1	100.00
		xbar_smoke_large_delays	41.280s	6.576ms	1	1	100.00
		xbar_smoke_slow_rsp	45.670s	5.268ms	1	1	100.00
		xbar_random_zero_delays	15.170s	256.643us	1	1	100.00
		xbar_random_large_delays	5.046m	49.483ms	1	1	100.00
		xbar_random_slow_rsp	4.120m	29.145ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	8.230s	259.160us	1	1	100.00
		xbar_error_and_unmapped_addr	14.830s	570.824us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	15.390s	316.261us	1	1	100.00
		xbar_error_and_unmapped_addr	14.830s	570.824us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.374m	3.390ms	1	1	100.00
		xbar_access_same_device_slow_rsp	36.070s	2.769ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	23.400s	357.891us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.268m	3.794ms	1	1	100.00
		xbar_stress_all_with_error	4.870m	16.174ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	42.080s	158.919us	1	1	100.00
		xbar_stress_all_with_reset_error	6.732m	13.968ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	42.433m	14.846ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	41.293m	31.990ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	44.485m	15.892ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	35.395m	11.819ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	43.154m	17.085ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	44.832m	15.773ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	43.971m	15.675ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.311m	16.262ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	17.210s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	16.640s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	20.750s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	20.060s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	17.950s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.890s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	18.140s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.680s	10.260us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.170s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	18.870s	10.280us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	19.540s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.630s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	22.790s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	20.370s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.430s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.630s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	21.080s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.460s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	18.220s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	22.690s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.870s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	22.150s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	19.070s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.190s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.390s	10.240us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	31.531m	11.075ms	1	1	100.00
		rom_e2e_asm_init_dev	42.382m	15.318ms	1	1	100.00
		rom_e2e_asm_init_prod	41.768m	20.084ms	1	1	100.00
		rom_e2e_asm_init_prod_end	40.355m	15.620ms	1	1	100.00
		rom_e2e_asm_init_rma	40.689m	14.723ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	38.692m	14.964ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	40.206m	16.070ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	40.021m	15.215ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	41.713m	17.201ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.962m	34.202ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.962m	34.202ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.102m	2.924ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.592m	2.345ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.059m	2.900ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.597m	2.905ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	14.656m	8.267ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.269m	3.128ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.909m	5.176ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	6.063m	5.230ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.203m	5.676ms	1	1	100.00
		chip_plic_all_irqs_10	4.667m	3.098ms	1	1	100.00
		chip_plic_all_irqs_20	6.895m	4.518ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.557m	3.675ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	14.929m	11.559ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.815m	3.609ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.204m	2.956ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	18.840m	8.066ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	18.116m	8.125ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.933m	8.002ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.452h	255.687ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.037m	3.845ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	3.728m	5.716ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.037m	3.845ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.817m	8.288ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	7.817m	8.288ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.109m	7.091ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.693m	4.422ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.596m	5.779ms	1	1	100.00
		chip_sw_aes_idle	2.597m	2.905ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.800m	2.978ms	1	1	100.00
		chip_sw_kmac_idle	2.233m	2.996ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.114m	3.015ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.981m	5.286ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	2.995m	4.756ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.991m	4.803ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	13.895m	10.308ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.303m	4.193ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.250m	4.681ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.226m	3.791ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.802m	4.299ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.841m	4.005ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.908m	5.325ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.082m	7.501ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	3.629m	6.095ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.226m	3.791ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.802m	4.299ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.271m	4.785ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	11.037m	6.467ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.849m	18.882ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.592m	2.345ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	8.130m	5.094ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.691m	2.939ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.732m	9.281ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.402m	3.081ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.321m	4.055ms	1	1	100.00
		chip_sw_clkmgr_jitter	1.996m	2.834ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.658m	2.633ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.813m	5.052ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	10.865m	7.306ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	51.345m	24.553ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.441m	2.866ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.685m	2.516ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	19.174m	12.255ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.462m	3.520ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.617m	5.118ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	18.969m	18.418ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.256h	139.126ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.082m	7.501ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.921m	4.889ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.553m	3.267ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	6.063m	5.230ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	18.840m	8.066ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	16.975m	7.947ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	1.978m	2.735ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.305m	6.249ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.494m	2.485ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	38.413m	14.783ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.698m	3.096ms	1	1	100.00
		chip_sw_edn_entropy_reqs	12.605m	6.234ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.698m	3.096ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	16.975m	7.947ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	2.439m	3.353ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	20.947m	24.110ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.239m	5.154ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	11.037m	6.467ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	6.080m	4.115ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.271m	4.785ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.040h	43.852ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	20.947m	24.110ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.626m	3.744ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	27.758m	12.734ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.855m	4.840ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.040h	43.852ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	3.855m	4.840ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.855m	4.840ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	3.855m	4.840ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	3.855m	4.840ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	6.063m	5.230ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	2.778m	5.825ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	8.725m	5.416ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	7.001m	6.441ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	7.001m	6.441ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.801m	2.993ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.691m	2.939ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.800m	2.978ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.184m	2.215ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.133m	3.750ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.806m	4.407ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	7.004m	5.063ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	5.883m	4.692ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	5.265m	4.021ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	27.758m	12.734ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	16.732m	9.281ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	11.388m	6.182ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	14.656m	8.267ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	37.937m	11.976ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.416m	2.366ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.408m	3.174ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.402m	3.081ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	27.758m	12.734ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	4.044m	4.931ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.828m	2.256ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	21.916m	9.442ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.233m	2.996ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.909m	5.176ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	15.834m	15.553ms	1	1	100.00
		chip_tap_straps_rma	1.476m	2.233ms	1	1	100.00
		chip_tap_straps_prod	17.562m	15.034ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.813m	3.622ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	4.044m	4.931ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	4.044m	4.931ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	4.044m	4.931ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	29.741m	13.129ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	3.855m	4.840ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.040h	43.852ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.692m	3.346ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.355m	6.105ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.052m	5.520ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.550m	6.901ms	0	1	0.00
		chip_sw_lc_ctrl_transition	4.044m	4.931ms	1	1	100.00
		chip_sw_keymgr_key_derivation	27.758m	12.734ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.726m	9.714ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.425m	7.443ms	1	1	100.00
		chip_prim_tl_access	2.778m	5.825ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	3.629m	6.095ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.303m	4.193ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	6.250m	4.681ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.226m	3.791ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.802m	4.299ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.841m	4.005ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.908m	5.325ms	1	1	100.00
		chip_tap_straps_dev	15.834m	15.553ms	1	1	100.00
		chip_tap_straps_rma	1.476m	2.233ms	1	1	100.00
		chip_tap_straps_prod	17.562m	15.034ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.318m	10.003ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	1.938m	3.315ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.537m	2.700ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.663m	3.239ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.841m	2.796ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	26.409m	33.717ms	1	1	100.00
		chip_rv_dm_lc_disabled	3.318m	10.003ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.069h	47.982ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	58.620m	48.665ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.059m	10.820ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.090h	47.379ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	26.409m	33.717ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	58.240s	2.679ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	55.160s	1.913ms	1	1	100.00
		rom_volatile_raw_unlock	1.010m	2.530ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	56.673m	17.135ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	58.849m	18.882ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.596m	5.779ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.596m	5.779ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.596m	5.779ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.873m	3.270ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	4.044m	4.931ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	20.947m	24.110ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.873m	3.270ms	1	1	100.00
		chip_sw_keymgr_key_derivation	27.758m	12.734ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.759m	4.523ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.809m	2.291ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	20.947m	24.110ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.873m	3.270ms	1	1	100.00
		chip_sw_keymgr_key_derivation	27.758m	12.734ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.759m	4.523ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	1.809m	2.291ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	4.044m	4.931ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.211m	4.479ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.813m	3.622ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.692m	3.346ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	8.355m	6.105ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	8.052m	5.520ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.550m	6.901ms	0	1	0.00
		chip_sw_lc_ctrl_transition	4.044m	4.931ms	1	1	100.00
		chip_prim_tl_access	2.778m	5.825ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.778m	5.825ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	17.672m	9.155ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.306m	8.217ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	20.102m	26.347ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.552m	7.519ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	5.165m	6.777ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.686m	6.818ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.078m	25.408ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	7.380m	9.819ms	0	1	0.00
		chip_sw_aon_timer_wdog_bite_reset	7.817m	8.288ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	11.831m	10.956ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	6.029m	4.966ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.306m	8.217ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.199m	4.302ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	3.850m	5.579ms	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.534m	5.830ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	4.275m	5.892ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	2.899m	4.861ms	0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.229m	8.006ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	19.738m	13.796ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	21.315m	20.379ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.947m	3.134ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	6.063m	5.230ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.726m	9.714ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.726m	9.714ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	19.738m	13.796ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	2.899m	4.861ms	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	6.029m	4.966ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	3.728m	5.716ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	3.091m	3.706ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	3.812m	4.506ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.953m	4.872ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	14.929m	11.559ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.022m	2.631ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	6.063m	5.230ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	18.116m	8.125ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.308m	4.912ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	9.024m	4.904ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.852m	3.183ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	1.809m	2.291ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	3.812m	4.506ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	3.812m	4.506ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	11.875m	11.808ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	15.260m	13.166ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	3.091m	3.706ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	4.746m	3.808ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	5.253m	6.506ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.476m	2.233ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	3.318m	10.003ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.203m	5.676ms	1	1	100.00
		chip_plic_all_irqs_10	4.667m	3.098ms	1	1	100.00
		chip_plic_all_irqs_20	6.895m	4.518ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	2.742m	2.469ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.103m	3.436ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	42.433m	14.846ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.894m	5.784ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.115m	3.232ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	3.642m	3.898ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.202m	3.375ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.759m	4.523ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.321m	4.055ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.719m	7.565ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	8.116m	9.153ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.425m	7.443ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	6.063m	5.230ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.824m	6.185ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.229m	8.006ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	18.892m	22.931ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.337m	3.190ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.510m	3.509ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	6.159m	4.559ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	18.892m	22.931ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	18.892m	22.931ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	39.464m	20.447ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	39.464m	20.447ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.871m	6.243ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.962m	34.202ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.827m	3.076ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.852m	2.137ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.064m	3.792ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	6.347m	4.133ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	16.572m	7.784ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.384h	31.634ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.775m	12.030ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	1.767m	2.552ms	1	1	100.00
V2		TOTAL			232	275	84.36
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.904m	2.334ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.379m	2.945ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.590h	71.495ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	8.515m	4.195ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	18.437m	11.860ms	1	1	100.00
		rom_e2e_jtag_debug_dev	2.788m	4.845ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.729m	12.044ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.708m	4.887ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.099m	4.299ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.540m	4.548ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.297s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.360m	4.687ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.094m	2.674ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	20.569m	7.338ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	17.070m	8.292ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.416m	2.154ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	10.483m	5.079ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.618m	2.652ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	2.115m	2.240ms	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	3.962m	6.268ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.162m	4.635ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	19.738m	13.796ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	18.437m	11.860ms	1	1	100.00
		rom_e2e_jtag_debug_dev	2.788m	4.845ms	0	1	0.00
		rom_e2e_jtag_debug_rma	19.729m	12.044ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	5.506m	5.738ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	6.063m	5.230ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.540h	37.602ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.540h	37.602ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.461m	3.190ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.148m	4.195ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	55.279m	19.044ms	1	1	100.00
V3		TOTAL			19	23	82.61
	Unmapped tests	chip_sival_flash_info_access	2.338m	3.030ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	5.446m	4.581ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	32.174m	33.412ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.228m	3.113ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.589m	2.705ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	3.690m	4.091ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.468s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.621m	3.448ms	1	1	100.00
		TOTAL			276	326	84.66

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.10698343534593818854654489582331253786764159518425327946785359378367179727205
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.109490515953908872797620850891766841463455462914268429448921170966394101767242
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.66779774413216000830621478860038065724646181751173029324242191323540148284680
    Line 490, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.44239924267069741219237935898579628137853227696279689197416216592871582105106
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.103362421427842554383247456709000918915725225143117372148590908688398875722219
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.109444770941235759732298703781210119234998321903067759730517706643117094340961
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.11984868686443948144112275404931999706421126133560418095497639675509276372938
    Line 493, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.110071332419873811708209484896769379430257248860227931463655957351667792095632
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.35320527597323352336290446439622165054914125050177478119834487158883744205184
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.81470384856932031410652275418669003735345453862033532110818154820593705975689
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 4 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.110401791723325716552201640498768088116734219947632911030217914185180409422239
    Line 405, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 4861.139000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 4861.139000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.73183632834528620270448508869619443683667479359004932857598349624535726606326
    Line 412, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 9818.919500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 9818.919500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.30038158125147885243872679876616473785192386071770798782346613667567482495212
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 6777.103000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 6777.103000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.71004603784676267352661217259004259344303266014950634434509695303012806295115
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 5578.555500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 5578.555500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.97749647776238043850801561176965900339908256240369064250556657498107760574895
    Line 482, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.21385767922949720283437370321307143042188939455827758676045009780038770759454
    Line 482, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.84653892419633952620042793933658813122264091444806048058360828932995558531715
    Line 474, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.91870696842780015280814467762921884066251630290485930012256495543493345081990
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2239.982772 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2239.982772 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.52207012789183600520327011556482481777576336215555303828369779870839206680403
    Line 389, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2735.149720 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2735.149720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.67890317826142113985948483001254141253980558522653041143197990104299562501094
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.145s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.80228162517909195094011436456879124192150258756301945230072479857241716929066
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.156s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.77605885661742985099501805118616791006832884476392410162062867790851110456887
    Line 539, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.36214974987980335251146619394668438496310812419999015080883439139102426896581
    Line 473, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.60709847748260659880670470358016175603823919278581911791020148044323874489719
    Line 552, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.114096081038596641409363844048219288947459122832954548239421089461394712312056
    Line 435, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.111694611864836340776410535539877261727410321429967016385935836520428922103878
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3231.843146 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3231.843146 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.49816420659018369182196479240612404694218104093690216138043793821456476663171
    Line 421, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 6901.018698 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 6901.018698 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.16398338637249824432652068688006906799321198276052695948365427799504073958187
    Line 434, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 33412.036644 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 33412.036644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@82762) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.104056384676110122061045337237676902201347997249847457950712636310994271633104
Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4505.681980 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@82762) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4505.681980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.92302240806971699283303428077077136767299679814075663204616493174634086060569
    Line 413, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34202.373454 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34202.373454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.25855119452679249735032481425946243725839674906913572216928848046335053777150
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3127.604431 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:292)] CHECK-fail: Expect alert 28!
  UVM_INFO @ 3127.604431 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.50881172589075305275168324749722856126096878112475733012034492584961967560352
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2955.958786 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2955.958786 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.64693301489154491466207606232556746990318955961696281674455644697049835447869
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.4578197176367746100897470381222140204934802816619366340946615971711069768988
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2215.491012 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2215.491012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@144772) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.42443081948511802768994199142387372535856112308199626055914643162080097934962
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3494.716365 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@144772) { a_addr: 'h105e8  a_data: 'h119b280f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2f  a_opcode: 'h4  a_user: 'h186ad  d_param: 'h0  d_source: 'h2f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3494.716365 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.17014823232393832090660114429301506283615385699038474519826090168910524828173
    Line 238, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 10003.305327 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x1044c read out mismatch
  UVM_INFO @ 10003.305327 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.22294423067023517627568588709681587500680364237669500944982796777301193366084
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3344.847500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3344.847500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.9028873098389336367830381571745817528156664557206257288435807359635957187542
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3176.387500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3176.387500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.115401080026941620652690235660153457727202918314803715082342805177514704455434
    Line 418, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 23044.654279 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 23044.654279 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.61602444048017378861619797655517319458408466279499884149355330679126531970676
    Line 457, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4195.388001 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 4195.388001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.18964094413462600938483196514871105452349512921335014710826956535491059266956
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.24936596775732900545678436193396327722258446761730611669357910231595370950668
    Line 492, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.44570069578680213135116179996959669274635997291268514266338633216499232128292
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_ERROR @ 4844.589968 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 4844.589968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32342) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.105897925893133177331392471600219983024477636839237778251907490642917695397264
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2173.213150 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32342) { a_addr: 'h106f4  a_data: 'hf8831e8e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8  a_opcode: 'h4  a_user: 'h1b62a  d_param: 'h0  d_source: 'h8  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2173.213150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---