ADC_CTRL Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	3.450s	5.822ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	3.320s	973.290us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.630s	533.376us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	1.494m	52.438ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	2.510s	1.373ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.590s	365.086us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.630s	533.376us	1	1	100.00
		adc_ctrl_csr_aliasing	2.510s	1.373ms	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	1.119m	164.987ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	8.486m	326.028ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	5.135m	331.484ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	6.297m	485.637ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	3.089m	417.212ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.643m	212.576ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	4.869m	163.084ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	1.451m	2.000s	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	8.270s	4.129ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	24.880s	26.773ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	41.320s	81.896ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	2.670m	366.940ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.110s	448.678us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	0.980s	374.364us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.980s	481.847us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.980s	481.847us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	3.320s	973.290us	1	1	100.00
		adc_ctrl_csr_rw	1.630s	533.376us	1	1	100.00
		adc_ctrl_csr_aliasing	2.510s	1.373ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.090s	2.323ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	3.320s	973.290us	1	1	100.00
		adc_ctrl_csr_rw	1.630s	533.376us	1	1	100.00
		adc_ctrl_csr_aliasing	2.510s	1.373ms	1	1	100.00
		adc_ctrl_same_csr_outstanding	3.090s	2.323ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	9.030s	4.392ms	1	1	100.00
		adc_ctrl_tl_intg_err	22.490s	8.683ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	22.490s	8.683ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	6.080s	4.901ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.115215170792415917908643152703871190988479661285306688051030994640903890838423
      Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---