EDN Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.860s	24.507us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.020s	30.367us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.990s	16.197us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	1.570s	37.853us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.090s	28.098us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.040s	68.553us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.990s	16.197us	1	1	100.00
		edn_csr_aliasing	1.090s	28.098us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.090s	56.342us	1	1	100.00
V2	csrng_commands	edn_genbits	1.090s	56.342us	1	1	100.00
V2	genbits	edn_genbits	1.090s	56.342us	1	1	100.00
V2	interrupts	edn_intr	0.930s	23.266us	1	1	100.00
V2	alerts	edn_alert	0.960s	25.878us	1	1	100.00
V2	errs	edn_err	0.890s	18.866us	1	1	100.00
V2	disable	edn_disable	0.970s	13.660us	1	1	100.00
		edn_disable_auto_req_mode	0.970s	49.630us	1	1	100.00
V2	stress_all	edn_stress_all	4.650s	698.432us	1	1	100.00
V2	intr_test	edn_intr_test	0.890s	46.341us	1	1	100.00
V2	alert_test	edn_alert_test	0.820s	44.415us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.360s	158.219us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.360s	158.219us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.020s	30.367us	1	1	100.00
		edn_csr_rw	0.990s	16.197us	1	1	100.00
		edn_csr_aliasing	1.090s	28.098us	1	1	100.00
		edn_same_csr_outstanding	0.940s	38.391us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.020s	30.367us	1	1	100.00
		edn_csr_rw	0.990s	16.197us	1	1	100.00
		edn_csr_aliasing	1.090s	28.098us	1	1	100.00
		edn_same_csr_outstanding	0.940s	38.391us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.250s	511.218us	1	1	100.00
		edn_tl_intg_err	1.310s	94.408us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.000s	20.960us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.960s	25.878us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.250s	511.218us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.250s	511.218us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.250s	511.218us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.250s	511.218us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.960s	25.878us	1	1	100.00
		edn_sec_cm	6.250s	511.218us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.960s	25.878us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.310s	94.408us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.011m	6.464ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00