HMAC Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 1.460s 137.459us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.740s 217.180us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.860s 55.201us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.030s 2.927ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.950s 157.077us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 6.333m 36.831ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.860s 55.201us 1 1 100.00
hmac_csr_aliasing 5.950s 157.077us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 45.900s 4.496ms 1 1 100.00
V2 back_pressure hmac_back_pressure 33.280s 1.576ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.020s 414.952us 1 1 100.00
hmac_test_sha384_vectors 5.790m 44.031ms 1 1 100.00
hmac_test_sha512_vectors 19.630s 944.227us 1 1 100.00
hmac_test_hmac256_vectors 5.900s 361.798us 1 1 100.00
hmac_test_hmac384_vectors 11.830s 345.838us 1 1 100.00
hmac_test_hmac512_vectors 13.350s 433.381us 1 1 100.00
V2 burst_wr hmac_burst_wr 25.750s 2.716ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 44.850s 2.673ms 1 1 100.00
V2 error hmac_error 38.940s 3.435ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.354m 36.186ms 1 1 100.00
V2 save_and_restore hmac_smoke 1.460s 137.459us 1 1 100.00
hmac_long_msg 45.900s 4.496ms 1 1 100.00
hmac_back_pressure 33.280s 1.576ms 1 1 100.00
hmac_datapath_stress 44.850s 2.673ms 1 1 100.00
hmac_burst_wr 25.750s 2.716ms 1 1 100.00
hmac_stress_all 12.605m 92.398ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 1.460s 137.459us 1 1 100.00
hmac_long_msg 45.900s 4.496ms 1 1 100.00
hmac_back_pressure 33.280s 1.576ms 1 1 100.00
hmac_datapath_stress 44.850s 2.673ms 1 1 100.00
hmac_wipe_secret 1.354m 36.186ms 1 1 100.00
hmac_test_sha256_vectors 8.020s 414.952us 1 1 100.00
hmac_test_sha384_vectors 5.790m 44.031ms 1 1 100.00
hmac_test_sha512_vectors 19.630s 944.227us 1 1 100.00
hmac_test_hmac256_vectors 5.900s 361.798us 1 1 100.00
hmac_test_hmac384_vectors 11.830s 345.838us 1 1 100.00
hmac_test_hmac512_vectors 13.350s 433.381us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 1.460s 137.459us 1 1 100.00
hmac_long_msg 45.900s 4.496ms 1 1 100.00
hmac_back_pressure 33.280s 1.576ms 1 1 100.00
hmac_datapath_stress 44.850s 2.673ms 1 1 100.00
hmac_burst_wr 25.750s 2.716ms 1 1 100.00
hmac_error 38.940s 3.435ms 1 1 100.00
hmac_wipe_secret 1.354m 36.186ms 1 1 100.00
hmac_test_sha256_vectors 8.020s 414.952us 1 1 100.00
hmac_test_sha384_vectors 5.790m 44.031ms 1 1 100.00
hmac_test_sha512_vectors 19.630s 944.227us 1 1 100.00
hmac_test_hmac256_vectors 5.900s 361.798us 1 1 100.00
hmac_test_hmac384_vectors 11.830s 345.838us 1 1 100.00
hmac_test_hmac512_vectors 13.350s 433.381us 1 1 100.00
hmac_stress_all 12.605m 92.398ms 1 1 100.00
V2 stress_all hmac_stress_all 12.605m 92.398ms 1 1 100.00
V2 alert_test hmac_alert_test 0.750s 15.103us 1 1 100.00
V2 intr_test hmac_intr_test 0.740s 24.674us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.780s 363.818us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.780s 363.818us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.740s 217.180us 1 1 100.00
hmac_csr_rw 0.860s 55.201us 1 1 100.00
hmac_csr_aliasing 5.950s 157.077us 1 1 100.00
hmac_same_csr_outstanding 1.870s 118.574us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.740s 217.180us 1 1 100.00
hmac_csr_rw 0.860s 55.201us 1 1 100.00
hmac_csr_aliasing 5.950s 157.077us 1 1 100.00
hmac_same_csr_outstanding 1.870s 118.574us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.940s 190.588us 1 1 100.00
hmac_tl_intg_err 3.060s 510.440us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.060s 510.440us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 1.460s 137.459us 1 1 100.00
V3 stress_reset hmac_stress_reset 5.390s 287.256us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.038m 15.033ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.460s 190.922us 1 1 100.00
TOTAL 28 28 100.00