I2C Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.085m	1.941ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	30.590s	1.393ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.710s	64.411us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.920s	28.342us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.730s	202.314us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.640s	231.535us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.040s	19.668us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.920s	28.342us	1	1	100.00
		i2c_csr_aliasing	1.640s	231.535us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.050s	76.438us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	2.482m	29.944ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	3.108m	25.052ms	1	1	100.00
V2	host_override	i2c_host_override	0.920s	21.857us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.615m	5.702ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	58.540s	5.605ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.040s	446.470us	1	1	100.00
		i2c_host_fifo_fmt_empty	2.570s	167.365us	1	1	100.00
		i2c_host_fifo_reset_rx	3.450s	1.345ms	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.470m	3.425ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	11.040s	891.801us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.350s	258.767us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.980s	907.397us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	43.920s	44.378ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	5.660s	744.013us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	22.130s	3.512ms	1	1	100.00
		i2c_target_intr_smoke	5.060s	777.887us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.340s	150.734us	1	1	100.00
		i2c_target_fifo_reset_tx	1.760s	559.021us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	2.289m	58.871ms	1	1	100.00
		i2c_target_stress_rd	22.130s	3.512ms	1	1	100.00
		i2c_target_intr_stress_wr	1.291m	9.335ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.660s	1.330ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	18.410s	10.012ms	0	1	0.00
V2	bad_address	i2c_target_bad_addr	4.980s	9.445ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	19.810s	10.004ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.350s	2.131ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.050s	34.211us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	3.108m	25.052ms	1	1	100.00
		i2c_host_perf_precise	2.310s	377.183us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	11.040s	891.801us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.200s	118.022us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.090s	2.311ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.300s	508.227us	1	1	100.00
		i2c_target_nack_txstretch	1.500s	738.758us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	10.910s	742.451us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.140s	468.596us	1	1	100.00
V2	alert_test	i2c_alert_test	0.850s	43.774us	1	1	100.00
V2	intr_test	i2c_intr_test	0.630s	58.467us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.220s	334.028us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.220s	334.028us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.710s	64.411us	1	1	100.00
		i2c_csr_rw	0.920s	28.342us	1	1	100.00
		i2c_csr_aliasing	1.640s	231.535us	1	1	100.00
		i2c_same_csr_outstanding	1.340s	29.196us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.710s	64.411us	1	1	100.00
		i2c_csr_rw	0.920s	28.342us	1	1	100.00
		i2c_csr_aliasing	1.640s	231.535us	1	1	100.00
		i2c_same_csr_outstanding	1.340s	29.196us	1	1	100.00
V2		TOTAL			31	38	81.58
V2S	tl_intg_err	i2c_tl_intg_err	1.460s	259.018us	1	1	100.00
		i2c_sec_cm	1.190s	69.686us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.460s	259.018us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	10.880s	1.348ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.320s	318.562us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	12.290s	3.482ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			40	50	80.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.42058520594677539531505393965501129406880190584685377295890856383742440117877
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  76437678 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  76437678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.49281572608830751343415870434403251100418858268459950643144749897628877273996
      Line 112, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 29944006962 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 29944006962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.112678336789107458256110911788315768946198066651116390549013909264757923890586
      Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1347856142 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1347856142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.40976087115582383052805020071536997792758102435008199410004842848911729428987
      Line 85, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3482128597 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3482128597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.105559201267187403933912204916696755147330585250358559834670355545621062026363
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 907397252 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 907397252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 1 failures:

  • Test i2c_target_stretch has 1 failures.

    • 0.i2c_target_stretch.96161662574813420042432282864080895224598978266220576049986872421037088162616
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stretch/latest/run.log

        UVM_FATAL @ 10011931154 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
        UVM_INFO @ 10011931154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.94645473675759273190637023439585073108308195046643799935659900663579272169739
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 318561605 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 318561605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.16771317546736549885664781139569379108180431970136492869045542976047499248106
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10003662003 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10003662003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.1873441907242109306842782345247889852888651449758019371678637084901986001280
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 258766863 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.108546616809600211075813672772870994811271493497942603603265119356760620829032
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 738758404 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 738758404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---