KEYMGR Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 2.040s 54.354us 1 1 100.00
V1 random keymgr_random 3.610s 253.236us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.960s 52.743us 1 1 100.00
V1 csr_rw keymgr_csr_rw 1.060s 12.588us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 16.970s 860.893us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 5.630s 544.032us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 0.890s 17.355us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.060s 12.588us 1 1 100.00
keymgr_csr_aliasing 5.630s 544.032us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 2.770s 188.650us 1 1 100.00
V2 sideload keymgr_sideload 1.770s 39.729us 1 1 100.00
keymgr_sideload_kmac 28.110s 1.579ms 1 1 100.00
keymgr_sideload_aes 1.900s 216.111us 1 1 100.00
keymgr_sideload_otbn 2.600s 121.584us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.640s 108.727us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.260s 99.808us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 2.060s 497.377us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 2.110s 227.702us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 1.930s 130.226us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 4.830s 418.461us 1 1 100.00
V2 stress_all keymgr_stress_all 2.663m 14.816ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.730s 66.236us 1 1 100.00
V2 alert_test keymgr_alert_test 0.690s 28.569us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 2.430s 572.945us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 2.430s 572.945us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.960s 52.743us 1 1 100.00
keymgr_csr_rw 1.060s 12.588us 1 1 100.00
keymgr_csr_aliasing 5.630s 544.032us 1 1 100.00
keymgr_same_csr_outstanding 1.650s 427.039us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.960s 52.743us 1 1 100.00
keymgr_csr_rw 1.060s 12.588us 1 1 100.00
keymgr_csr_aliasing 5.630s 544.032us 1 1 100.00
keymgr_same_csr_outstanding 1.650s 427.039us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 3.800s 818.093us 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 3.800s 818.093us 1 1 100.00
keymgr_tl_intg_err 4.260s 969.315us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 1.870s 674.767us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 1.870s 674.767us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 1.870s 674.767us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 1.870s 674.767us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 5.350s 220.671us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 3.800s 818.093us 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 3.800s 818.093us 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 4.260s 969.315us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 1.870s 674.767us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.770s 188.650us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 3.610s 253.236us 1 1 100.00
keymgr_csr_rw 1.060s 12.588us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 3.610s 253.236us 1 1 100.00
keymgr_csr_rw 1.060s 12.588us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 3.610s 253.236us 1 1 100.00
keymgr_csr_rw 1.060s 12.588us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.260s 99.808us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 1.930s 130.226us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 1.930s 130.226us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 3.610s 253.236us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 1.750s 51.163us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 3.800s 818.093us 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 3.800s 818.093us 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 3.800s 818.093us 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 1.640s 103.500us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.260s 99.808us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 3.800s 818.093us 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 3.800s 818.093us 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 3.800s 818.093us 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 1.640s 103.500us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 1.640s 103.500us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 3.800s 818.093us 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 1.640s 103.500us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 3.800s 818.093us 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 1.640s 103.500us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 5.030s 437.606us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00