KMAC/UNMASKED Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	15.600s	752.414us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.020s	105.994us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.110s	103.596us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	12.770s	4.002ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.530s	205.034us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.820s	35.686us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.110s	103.596us	1	1	100.00
		kmac_csr_aliasing	3.530s	205.034us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.800s	12.420us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.460s	21.471us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	15.639m	37.711ms	1	1	100.00
V2	burst_write	kmac_burst_write	30.330s	477.496us	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	28.230s	646.054us	1	1	100.00
		kmac_test_vectors_sha3_256	30.640s	9.367ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.440s	434.731us	1	1	100.00
		kmac_test_vectors_sha3_512	11.660s	1.143ms	1	1	100.00
		kmac_test_vectors_shake_128	35.365m	211.079ms	1	1	100.00
		kmac_test_vectors_shake_256	1.663m	6.968ms	1	1	100.00
		kmac_test_vectors_kmac	2.150s	86.530us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.060s	44.121us	1	1	100.00
V2	sideload	kmac_sideload	4.491m	15.954ms	1	1	100.00
V2	app	kmac_app	4.484m	67.315ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	44.380s	8.192ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.089m	25.670ms	1	1	100.00
V2	error	kmac_error	3.207m	3.782ms	1	1	100.00
V2	key_error	kmac_key_error	1.170s	124.939us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.550s	857.738us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	17.800s	270.236us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	14.540s	279.068us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	19.740s	2.262ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	10.710s	1.098ms	1	1	100.00
V2	stress_all	kmac_stress_all	40.822m	193.994ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.870s	16.212us	1	1	100.00
V2	alert_test	kmac_alert_test	1.100s	18.775us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.210s	375.964us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.210s	375.964us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.020s	105.994us	1	1	100.00
		kmac_csr_rw	1.110s	103.596us	1	1	100.00
		kmac_csr_aliasing	3.530s	205.034us	1	1	100.00
		kmac_same_csr_outstanding	2.500s	178.352us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.020s	105.994us	1	1	100.00
		kmac_csr_rw	1.110s	103.596us	1	1	100.00
		kmac_csr_aliasing	3.530s	205.034us	1	1	100.00
		kmac_same_csr_outstanding	2.500s	178.352us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.260s	71.364us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.260s	71.364us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.260s	71.364us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.260s	71.364us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.140s	128.412us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	44.490s	68.247ms	1	1	100.00
		kmac_tl_intg_err	3.140s	452.559us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.140s	452.559us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	10.710s	1.098ms	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	15.600s	752.414us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.491m	15.954ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.260s	71.364us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	44.490s	68.247ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	44.490s	68.247ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	44.490s	68.247ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	15.600s	752.414us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	10.710s	1.098ms	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	44.490s	68.247ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.714m	6.165ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	15.600s	752.414us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.590s	2.045ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.90774923372156478266715256792278838951163066556456590245237174065908582457852
      Line 309, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

        UVM_ERROR @ 128411600 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1598431720 [0x5f4621e8] vs 2924256314 [0xae4c9c3a]) Regname: kmac_reg_block.prefix_10 reset value: 0x0
        UVM_INFO @ 128411600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---