ea78273| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0.770s | 75.304us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.590s | 39.374us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.750s | 21.072us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 1.120s | 223.940us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.630s | 19.137us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.260s | 86.319us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.750s | 21.072us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.630s | 19.137us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 1.000s | 413.674us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 0.730s | 544.883us | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 9.090s | 36.165ms | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 9.090s | 36.165ms | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 0.710s | 283.776us | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.630s | 21.212us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.720s | 26.842us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 2.050s | 48.579us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 2.050s | 48.579us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.590s | 39.374us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.750s | 21.072us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.630s | 19.137us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.760s | 101.826us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.590s | 39.374us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.750s | 21.072us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.630s | 19.137us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.760s | 101.826us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.750s | 49.494us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 1.050s | 78.977us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.050s | 78.977us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 0.810s | 221.383us | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.720s | 113.162us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 14.790s | 1.966ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 3 | 33.33 | |||
| TOTAL | 16 | 19 | 84.21 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.101211903646921853615015871190398561039685410839788485277733999135351682364899
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 221382634 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc3d5a504) == 0x1
UVM_INFO @ 221382634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.60406524527283585676098720361608734183025805318136945893834295114221877124330
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 413674446 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x8e4a3904) == 0x1
UVM_INFO @ 413674446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.83412351467854607031445712512301504900374740723903019382010407221926887830726
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 113162452 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 113162452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---