SPI_DEVICE/1R1W Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	35.440s	2.290ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.290s	224.063us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.860s	84.169us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.890s	536.408us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	9.600s	631.615us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.400s	678.212us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.860s	84.169us	1	1	100.00
		spi_device_csr_aliasing	9.600s	631.615us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.880s	30.080us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.570s	109.119us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.890s	13.611us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.880s	2.365us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.720s	6.413us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.100s	14.985us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.100s	14.985us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.270s	3.981ms	1	1	100.00
		spi_device_tpm_sts_read	0.740s	33.528us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.740s	5.552ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	9.170s	60.674ms	1	1	100.00
		spi_device_flash_all	32.410s	2.945ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	14.060s	10.456ms	1	1	100.00
		spi_device_flash_all	32.410s	2.945ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	14.060s	10.456ms	1	1	100.00
		spi_device_flash_all	32.410s	2.945ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	32.410s	2.945ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.900s	443.897us	1	1	100.00
		spi_device_flash_all	32.410s	2.945ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.900s	443.897us	1	1	100.00
		spi_device_flash_all	32.410s	2.945ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.900s	443.897us	1	1	100.00
		spi_device_flash_all	32.410s	2.945ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.900s	443.897us	1	1	100.00
		spi_device_flash_all	32.410s	2.945ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.900s	443.897us	1	1	100.00
		spi_device_flash_all	32.410s	2.945ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	1.830s	58.055us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	58.090s	7.450ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	58.090s	7.450ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	58.090s	7.450ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.250s	81.663us	1	1	100.00
		spi_device_read_buffer_direct	8.590s	2.933ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	58.090s	7.450ms	1	1	100.00
		spi_device_flash_all	32.410s	2.945ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	32.410s	2.945ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	32.410s	2.945ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.620s	202.328us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.620s	202.328us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	35.440s	2.290ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.573m	8.697ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.070s	66.943us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.680s	46.949us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.930s	18.168us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.350s	177.770us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.350s	177.770us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.290s	224.063us	1	1	100.00
		spi_device_csr_rw	1.860s	84.169us	1	1	100.00
		spi_device_csr_aliasing	9.600s	631.615us	1	1	100.00
		spi_device_same_csr_outstanding	1.650s	61.448us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.290s	224.063us	1	1	100.00
		spi_device_csr_rw	1.860s	84.169us	1	1	100.00
		spi_device_csr_aliasing	9.600s	631.615us	1	1	100.00
		spi_device_same_csr_outstanding	1.650s	61.448us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.160s	106.003us	1	1	100.00
		spi_device_tl_intg_err	5.880s	333.495us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.880s	333.495us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.575m	37.324ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.107599607844373927110546942889217457187684008375205859757375294852749826029705
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2005446 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[70])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2005446 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2005446 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[966])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.92639074597012227971779109897544316551704434834172700232449827305008216891631
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   3979001 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa255ac [101000100101010110101100] vs 0x0 [0])
        UVM_ERROR @   4070001 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfdd9ce [111111011101100111001110] vs 0x0 [0])
        UVM_ERROR @   4131001 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb11f09 [101100010001111100001001] vs 0x0 [0])
        UVM_ERROR @   4198001 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x884bf6 [100010000100101111110110] vs 0x0 [0])
        UVM_ERROR @   4279001 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf1ae7e [111100011010111001111110] vs 0x0 [0])