SPI_DEVICE/2P Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	51.790s	5.941ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.160s	129.388us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.030s	131.187us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	22.560s	604.829us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	14.110s	366.315us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.660s	53.247us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.030s	131.187us	1	1	100.00
		spi_device_csr_aliasing	14.110s	366.315us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.760s	73.566us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.420s	60.092us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.800s	22.234us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.040s	52.602us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	26.386us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.050s	112.380us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.050s	112.380us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	11.700s	14.137ms	1	1	100.00
		spi_device_tpm_sts_read	0.790s	185.471us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	6.790s	2.158ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.930s	554.092us	1	1	100.00
		spi_device_flash_all	20.270s	4.635ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.950s	44.595us	1	1	100.00
		spi_device_flash_all	20.270s	4.635ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.950s	44.595us	1	1	100.00
		spi_device_flash_all	20.270s	4.635ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	20.270s	4.635ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	25.820s	16.145ms	1	1	100.00
		spi_device_flash_all	20.270s	4.635ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	25.820s	16.145ms	1	1	100.00
		spi_device_flash_all	20.270s	4.635ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	25.820s	16.145ms	1	1	100.00
		spi_device_flash_all	20.270s	4.635ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	25.820s	16.145ms	1	1	100.00
		spi_device_flash_all	20.270s	4.635ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	25.820s	16.145ms	1	1	100.00
		spi_device_flash_all	20.270s	4.635ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.540s	1.729ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	7.360s	1.494ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	7.360s	1.494ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	7.360s	1.494ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	2.540s	228.272us	1	1	100.00
		spi_device_read_buffer_direct	7.340s	2.011ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	7.360s	1.494ms	1	1	100.00
		spi_device_flash_all	20.270s	4.635ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	20.270s	4.635ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	20.270s	4.635ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	6.910s	7.568ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	6.910s	7.568ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	51.790s	5.941ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	37.800s	3.790ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.040s	57.591us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.790s	26.128us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.730s	23.481us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.540s	64.157us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.540s	64.157us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.160s	129.388us	1	1	100.00
		spi_device_csr_rw	1.030s	131.187us	1	1	100.00
		spi_device_csr_aliasing	14.110s	366.315us	1	1	100.00
		spi_device_same_csr_outstanding	2.170s	83.586us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.160s	129.388us	1	1	100.00
		spi_device_csr_rw	1.030s	131.187us	1	1	100.00
		spi_device_csr_aliasing	14.110s	366.315us	1	1	100.00
		spi_device_same_csr_outstanding	2.170s	83.586us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	0.870s	39.537us	1	1	100.00
		spi_device_tl_intg_err	5.870s	398.463us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.870s	398.463us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	13.150s	4.740ms	1	1	100.00
		TOTAL			33	33	100.00