SPI_HOST Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	35.000s	1.165ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	29.749us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	20.919us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	234.970us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	85.970us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	31.895us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	20.919us	1	1	100.00
		spi_host_csr_aliasing	5.000s	85.970us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	16.721us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	39.146us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	2.000s	22.062us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.000s	130.053us	1	1	100.00
		spi_host_error_cmd	2.000s	35.101us	1	1	100.00
		spi_host_event	9.000s	1.959ms	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	345.245us	1	1	100.00
V2	speed	spi_host_speed	3.000s	345.245us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	345.245us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	3.000s	71.040us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	2.000s	74.683us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	345.245us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	345.245us	1	1	100.00
V2	duplex	spi_host_smoke	35.000s	1.165ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	35.000s	1.165ms	1	1	100.00
V2	stress_all	spi_host_stress_all	2.000s	231.699us	1	1	100.00
V2	spien	spi_host_spien	3.000s	241.958us	1	1	100.00
V2	stall	spi_host_status_stall	6.000s	2.621ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	416.681us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.000s	130.053us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	24.954us	1	1	100.00
V2	intr_test	spi_host_intr_test	6.000s	16.431us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	9.000s	250.865us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	9.000s	250.865us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	29.749us	1	1	100.00
		spi_host_csr_rw	5.000s	20.919us	1	1	100.00
		spi_host_csr_aliasing	5.000s	85.970us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	140.253us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	29.749us	1	1	100.00
		spi_host_csr_rw	5.000s	20.919us	1	1	100.00
		spi_host_csr_aliasing	5.000s	85.970us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	140.253us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	73.437us	1	1	100.00
		spi_host_sec_cm	2.000s	1.969ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	73.437us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.100m	2.824ms	1	1	100.00
		TOTAL			26	26	100.00