SRAM_CTRL/MAIN Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	15.600s	9.967ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.810s	30.752us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.920s	15.670us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.360s	354.619us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.700s	57.017us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.160s	370.302us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.920s	15.670us	1	1	100.00
		sram_ctrl_csr_aliasing	0.700s	57.017us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.905m	52.581ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.834m	22.067ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.236m	6.771ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.160m	8.609ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	13.871m	615.597ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	37.640s	1.101ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	37.800s	18.058ms	1	1	100.00
V2	executable	sram_ctrl_executable	6.489m	88.488ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	16.230s	2.440ms	1	1	100.00
		sram_ctrl_partial_access_b2b	7.799m	25.419ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	54.020s	1.078ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	11.740s	2.901ms	1	1	100.00
		sram_ctrl_throughput_w_readback	15.250s	800.868us	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.275m	13.155ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.400s	691.872us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	58.471m	69.957ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.990s	12.816us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.020s	227.325us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.020s	227.325us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.810s	30.752us	1	1	100.00
		sram_ctrl_csr_rw	0.920s	15.670us	1	1	100.00
		sram_ctrl_csr_aliasing	0.700s	57.017us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.770s	39.247us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.810s	30.752us	1	1	100.00
		sram_ctrl_csr_rw	0.920s	15.670us	1	1	100.00
		sram_ctrl_csr_aliasing	0.700s	57.017us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.770s	39.247us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.100s	3.896ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.750s	6.118us	0	1	0.00
		sram_ctrl_tl_intg_err	2.110s	415.944us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.750s	6.118us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.110s	415.944us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.275m	13.155ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.275m	13.155ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.920s	15.670us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	6.489m	88.488ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	6.489m	88.488ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	6.489m	88.488ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	37.800s	18.058ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.040s	711.534us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.100s	3.896ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	7.700s	1.355ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	15.600s	9.967ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	15.600s	9.967ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	6.489m	88.488ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.750s	6.118us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	37.800s	18.058ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.750s	6.118us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.750s	6.118us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	15.600s	9.967ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.750s	6.118us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	29.960s	1.315ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.49028730679246120315456872043187552849473014251427391943418797646745815530641
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6117604 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6117604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---