SRAM_CTRL/RET Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.410s	951.413us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.640s	32.081us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.610s	38.046us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.410s	49.810us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.620s	39.898us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.850s	55.943us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.610s	38.046us	1	1	100.00
		sram_ctrl_csr_aliasing	0.620s	39.898us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.680s	690.399us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.300s	103.162us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	36.760s	1.176ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.523m	5.838ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	29.050s	5.436ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.425m	16.419ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.100s	2.195ms	1	1	100.00
V2	executable	sram_ctrl_executable	2.283m	2.920ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	2.850s	362.453us	1	1	100.00
		sram_ctrl_partial_access_b2b	2.145m	2.512ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	26.760s	119.237us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	0.880s	568.027us	1	1	100.00
		sram_ctrl_throughput_w_readback	13.730s	318.855us	1	1	100.00
V2	regwen	sram_ctrl_regwen	6.093m	14.632ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.660s	109.840us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	15.134m	64.948ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.700s	52.773us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.060s	308.011us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.060s	308.011us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.640s	32.081us	1	1	100.00
		sram_ctrl_csr_rw	0.610s	38.046us	1	1	100.00
		sram_ctrl_csr_aliasing	0.620s	39.898us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	63.698us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.640s	32.081us	1	1	100.00
		sram_ctrl_csr_rw	0.610s	38.046us	1	1	100.00
		sram_ctrl_csr_aliasing	0.620s	39.898us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.710s	63.698us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.440s	395.884us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.580s	4.912us	0	1	0.00
		sram_ctrl_tl_intg_err	1.900s	381.411us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.580s	4.912us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.900s	381.411us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	6.093m	14.632ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	6.093m	14.632ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.610s	38.046us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.283m	2.920ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.283m	2.920ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.283m	2.920ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.100s	2.195ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.830s	68.733us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.440s	395.884us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.790s	35.798us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.410s	951.413us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.410s	951.413us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.283m	2.920ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.580s	4.912us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.100s	2.195ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.580s	4.912us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.580s	4.912us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.410s	951.413us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.580s	4.912us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.267m	4.784ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.62430313758278275632015536022793921411761780252289955418236384137596897951984
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   4911710 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   4911710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---