SYSRST_CTRL Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 4.700s 2.113ms 1 1 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 3.120s 2.459ms 1 1 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 2.240s 2.427ms 1 1 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.950s 2.566ms 1 1 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 8.650s 4.014ms 1 1 100.00
V1 csr_rw sysrst_ctrl_csr_rw 2.970s 2.056ms 1 1 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 1.214m 38.842ms 1 1 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 4.410s 2.871ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 1.940s 2.192ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 2.970s 2.056ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.410s 2.871ms 1 1 100.00
V1 TOTAL 9 9 100.00
V2 combo_detect sysrst_ctrl_combo_detect 34.440s 67.598ms 1 1 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 2.556m 80.015ms 1 1 100.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 1.130s 3.394ms 1 1 100.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 4.970s 4.213ms 1 1 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 6.090s 2.513ms 1 1 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 1.620s 2.223ms 1 1 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 7.390s 3.696ms 1 1 100.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 1.210s 2.684ms 1 1 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 2.060s 2.986ms 1 1 100.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 19.720s 39.589ms 1 1 100.00
V2 stress_all sysrst_ctrl_stress_all 5.980s 7.007ms 1 1 100.00
V2 alert_test sysrst_ctrl_alert_test 2.430s 2.025ms 1 1 100.00
V2 intr_test sysrst_ctrl_intr_test 4.430s 2.012ms 1 1 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 3.500s 2.401ms 1 1 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 3.500s 2.401ms 1 1 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 8.650s 4.014ms 1 1 100.00
sysrst_ctrl_csr_rw 2.970s 2.056ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.410s 2.871ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 15.890s 10.035ms 1 1 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 8.650s 4.014ms 1 1 100.00
sysrst_ctrl_csr_rw 2.970s 2.056ms 1 1 100.00
sysrst_ctrl_csr_aliasing 4.410s 2.871ms 1 1 100.00
sysrst_ctrl_same_csr_outstanding 15.890s 10.035ms 1 1 100.00
V2 TOTAL 15 15 100.00
V2S tl_intg_err sysrst_ctrl_sec_cm 22.770s 22.016ms 1 1 100.00
sysrst_ctrl_tl_intg_err 28.700s 42.745ms 1 1 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 28.700s 42.745ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 6.720s 3.321ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 27 27 100.00