UART Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: ea78273

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.690s	672.923us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.170s	1.034ms	1	1	100.00
V1	csr_rw	uart_csr_rw	0.890s	35.531us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.090s	560.594us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.880s	31.632us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.030s	180.007us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.890s	35.531us	1	1	100.00
		uart_csr_aliasing	0.880s	31.632us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	19.470s	192.557ms	1	1	100.00
V2	parity	uart_smoke	1.690s	672.923us	1	1	100.00
		uart_tx_rx	19.470s	192.557ms	1	1	100.00
V2	parity_error	uart_intr	39.630s	54.086ms	1	1	100.00
		uart_rx_parity_err	18.070s	60.247ms	1	1	100.00
V2	watermark	uart_tx_rx	19.470s	192.557ms	1	1	100.00
		uart_intr	39.630s	54.086ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.160m	103.263ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	30.090s	22.209ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	2.420m	98.844ms	1	1	100.00
V2	rx_frame_err	uart_intr	39.630s	54.086ms	1	1	100.00
V2	rx_break_err	uart_intr	39.630s	54.086ms	1	1	100.00
V2	rx_timeout	uart_intr	39.630s	54.086ms	1	1	100.00
V2	perf	uart_perf	8.119m	14.738ms	1	1	100.00
V2	sys_loopback	uart_loopback	11.410s	9.666ms	1	1	100.00
V2	line_loopback	uart_loopback	11.410s	9.666ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	11.700s	18.803ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.980s	2.307ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.660s	874.063us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	2.780s	4.495ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.846m	76.484ms	1	1	100.00
V2	stress_all	uart_stress_all	8.346m	210.557ms	1	1	100.00
V2	alert_test	uart_alert_test	0.650s	37.534us	1	1	100.00
V2	intr_test	uart_intr_test	0.850s	22.469us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.860s	96.252us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.860s	96.252us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.170s	1.034ms	1	1	100.00
		uart_csr_rw	0.890s	35.531us	1	1	100.00
		uart_csr_aliasing	0.880s	31.632us	1	1	100.00
		uart_same_csr_outstanding	0.700s	30.162us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.170s	1.034ms	1	1	100.00
		uart_csr_rw	0.890s	35.531us	1	1	100.00
		uart_csr_aliasing	0.880s	31.632us	1	1	100.00
		uart_same_csr_outstanding	0.700s	30.162us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	0.860s	37.599us	1	1	100.00
		uart_tl_intg_err	1.380s	109.260us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.380s	109.260us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	23.730s	3.534ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00