CHIP Simulation Results

Thursday October 23 2025 19:26:26 UTC

GitHub Revision: `ea78273`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.234m	3.096ms	1	1	100.00
		chip_sw_example_rom	57.720s	2.271ms	1	1	100.00
		chip_sw_example_manufacturer	2.182m	3.440ms	1	1	100.00
		chip_sw_example_concurrency	2.522m	2.941ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	3.859m	7.188ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.283m	4.358ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	4.876m	5.585ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	1.065h	32.195ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	9.367m	11.910ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.065h	32.195ms	1	1	100.00
		chip_csr_rw	3.283m	4.358ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	6.530s	159.380us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.054m	4.183ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.054m	4.183ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.054m	4.183ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	6.988m	4.580ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	6.988m	4.580ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	5.520m	3.842ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	5.005m	4.374ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.918m	4.253ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	5.225m	4.267ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	17.276m	8.980ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	5.080m	4.824ms	1	1	100.00
V1		TOTAL			18	18	100.00
V2	chip_pin_mux	chip_padctrl_attributes	3.223m	5.221ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.223m	5.221ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	3.257m	3.306ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	5.367m	6.505ms	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.458m	4.058ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	2.000m	3.107ms	1	1	100.00
		chip_tap_straps_testunlock0	3.171m	4.061ms	1	1	100.00
		chip_tap_straps_rma	1.478m	2.427ms	1	1	100.00
		chip_tap_straps_prod	1.657m	2.007ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.035m	3.014ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	12.839m	8.498ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	7.176m	5.219ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	7.176m	5.219ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	9.430m	8.496ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	32.603m	19.807ms	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.487m	3.908ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.769m	5.579ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.302m	18.347ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.939m	3.167ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.571m	6.556ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.910m	3.323ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.988m	8.313ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.885m	2.953ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.704m	4.696ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.451m	2.942ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	2.273m	2.495ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	4.533m	5.302ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.235m	5.151ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	2.625m	2.749ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	4.235m	5.151ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.650m	2.998ms	1	1	100.00
		chip_sw_aes_smoketest	3.603m	3.459ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.028m	2.495ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.773m	2.352ms	1	1	100.00
		chip_sw_csrng_smoketest	2.135m	2.442ms	1	1	100.00
		chip_sw_entropy_src_smoketest	10.997m	5.563ms	1	1	100.00
		chip_sw_gpio_smoketest	3.158m	3.573ms	1	1	100.00
		chip_sw_hmac_smoketest	4.212m	2.848ms	1	1	100.00
		chip_sw_kmac_smoketest	3.154m	3.492ms	1	1	100.00
		chip_sw_otbn_smoketest	20.553m	10.721ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.580m	5.830ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.787m	5.639ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.668m	2.967ms	1	1	100.00
		chip_sw_rv_timer_smoketest	1.675m	2.299ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.896m	2.846ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.436m	2.455ms	1	1	100.00
		chip_sw_uart_smoketest	3.121m	2.936ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.874m	2.676ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	6.746m	4.459ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.133h	60.097ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	42.758m	14.529ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	2.567m	5.332ms	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.768m	3.518ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.630m	2.897ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.941h	54.303ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.963h	56.896ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	4.999m	5.213ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	4.999m	5.213ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.065h	32.195ms	1	1	100.00
		chip_same_csr_outstanding	28.874m	16.828ms	1	1	100.00
		chip_csr_hw_reset	3.859m	7.188ms	1	1	100.00
		chip_csr_rw	3.283m	4.358ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.065h	32.195ms	1	1	100.00
		chip_same_csr_outstanding	28.874m	16.828ms	1	1	100.00
		chip_csr_hw_reset	3.859m	7.188ms	1	1	100.00
		chip_csr_rw	3.283m	4.358ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	17.310s	657.547us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	6.310s	41.910us	1	1	100.00
		xbar_smoke_large_delays	1.039m	10.571ms	1	1	100.00
		xbar_smoke_slow_rsp	50.490s	4.791ms	1	1	100.00
		xbar_random_zero_delays	6.030s	42.911us	1	1	100.00
		xbar_random_large_delays	1.520m	14.476ms	1	1	100.00
		xbar_random_slow_rsp	3.896m	27.151ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	35.590s	1.348ms	1	1	100.00
		xbar_error_and_unmapped_addr	8.460s	249.546us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	6.020s	149.682us	1	1	100.00
		xbar_error_and_unmapped_addr	8.460s	249.546us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	9.460s	242.635us	1	1	100.00
		xbar_access_same_device_slow_rsp	4.254m	28.708ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	24.160s	481.572us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.622m	4.129ms	1	1	100.00
		xbar_stress_all_with_error	2.068m	2.696ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	3.987m	2.998ms	1	1	100.00
		xbar_stress_all_with_reset_error	5.637m	12.474ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	42.758m	14.529ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	38.384m	29.079ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	42.156m	18.264ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	35.024m	11.263ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	42.877m	15.896ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	42.015m	15.758ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	42.358m	16.125ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.848m	15.565ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	20.740s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	17.290s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	22.660s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	25.460s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	28.570s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	17.440s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	24.740s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	17.500s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	22.000s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	18.160s	10.100us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.540s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	16.440s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	19.700s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	21.860s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	18.790s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	22.750s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	19.290s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.660s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	16.800s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.380s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.400s	10.280us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.810s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.310s	10.200us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.360s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.200s	10.360us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	33.426m	12.550ms	1	1	100.00
		rom_e2e_asm_init_dev	42.560m	15.024ms	1	1	100.00
		rom_e2e_asm_init_prod	42.093m	15.735ms	1	1	100.00
		rom_e2e_asm_init_prod_end	40.915m	15.812ms	1	1	100.00
		rom_e2e_asm_init_rma	40.368m	17.173ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	42.447m	18.018ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	40.170m	14.432ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	39.506m	15.066ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	43.657m	18.748ms	0	1	0.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.746m	34.761ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.746m	34.761ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	2.190m	2.536ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.939m	3.167ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.188m	2.806ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.234m	2.380ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	28.029m	13.383ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.238m	3.001ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	4.998m	4.757ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	5.914m	5.089ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.033m	5.217ms	1	1	100.00
		chip_plic_all_irqs_10	4.496m	3.396ms	1	1	100.00
		chip_plic_all_irqs_20	6.942m	5.093ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.601m	3.229ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.567m	10.548ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	3.040m	3.623ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.816m	2.938ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	21.126m	9.150ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	19.587m	8.949ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.587m	7.375ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.089h	255.789ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	4.235m	3.387ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.580m	5.830ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	4.235m	3.387ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.400m	7.565ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	8.400m	7.565ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	4.200m	7.146ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	4.358m	5.180ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	10.143m	5.504ms	1	1	100.00
		chip_sw_aes_idle	2.234m	2.380ms	1	1	100.00
		chip_sw_hmac_enc_idle	2.742m	2.580ms	1	1	100.00
		chip_sw_kmac_idle	2.076m	2.525ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	4.192m	4.252ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	3.493m	4.116ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.063m	4.647ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	4.470m	3.614ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	14.617m	12.235ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.039m	4.414ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.188m	5.242ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.913m	4.715ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.938m	4.493ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.999m	4.217ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.453m	4.918ms	1	1	100.00
		chip_sw_ast_clk_outputs	9.430m	8.496ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	4.742m	4.859ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.913m	4.715ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.938m	4.493ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	5.487m	3.908ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.769m	5.579ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.302m	18.347ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.939m	3.167ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.571m	6.556ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.910m	3.323ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.988m	8.313ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.885m	2.953ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.704m	4.696ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.451m	2.942ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.990m	2.520ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	5.680m	4.515ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	9.688m	6.882ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	52.003m	25.044ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	3.092m	3.243ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.591m	2.866ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	9.870m	8.155ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.742m	3.364ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.191m	4.837ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	16.337m	18.496ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.618h	154.426ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	9.430m	8.496ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	6.696m	4.867ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	4.127m	3.853ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	5.914m	5.089ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	21.126m	9.150ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.078m	6.311ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.457m	2.209ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.066m	5.985ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.855m	2.806ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	59.277m	21.373ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.148m	2.907ms	1	1	100.00
		chip_sw_edn_entropy_reqs	13.443m	7.122ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.148m	2.907ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.078m	6.311ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.896m	2.233ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	20.671m	21.250ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	10.005m	5.399ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	10.769m	5.579ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.607m	3.747ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	5.487m	3.908ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.001h	42.468ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	20.671m	21.250ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.963m	3.860ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	24.936m	11.940ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.901m	5.047ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.001h	42.468ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	5.901m	5.047ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.901m	5.047ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	5.901m	5.047ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	5.901m	5.047ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	5.914m	5.089ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	3.698m	9.494ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.332m	4.771ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.958m	5.708ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.958m	5.708ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	2.490m	2.874ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.910m	3.323ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	2.742m	2.580ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	1.861m	3.094ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.569m	4.239ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	4.931m	4.307ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	5.187m	4.255ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.170m	6.037ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	4.800m	3.993ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	24.936m	11.940ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.988m	8.313ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	21.302m	9.841ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	28.029m	13.383ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	43.839m	14.295ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.601m	2.559ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.981m	3.422ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	2.885m	2.953ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	24.936m	11.940ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	8.436m	12.865ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.873m	2.669ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	21.979m	10.012ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.076m	2.525ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	4.998m	4.757ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	2.000m	3.107ms	1	1	100.00
		chip_tap_straps_rma	1.478m	2.427ms	1	1	100.00
		chip_tap_straps_prod	1.657m	2.007ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.719m	2.812ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	8.436m	12.865ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	8.436m	12.865ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	8.436m	12.865ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	14.626m	8.764ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	5.901m	5.047ms	1	1	100.00
		chip_sw_flash_rma_unlocked	1.001h	42.468ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.698m	3.601ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.626m	6.736ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.195m	6.959ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.976m	7.452ms	0	1	0.00
		chip_sw_lc_ctrl_transition	8.436m	12.865ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.936m	11.940ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	5.127m	8.853ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	6.803m	7.134ms	1	1	100.00
		chip_prim_tl_access	3.698m	9.494ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	4.742m	4.859ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.039m	4.414ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.188m	5.242ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	6.913m	4.715ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.938m	4.493ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	6.999m	4.217ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.453m	4.918ms	1	1	100.00
		chip_tap_straps_dev	2.000m	3.107ms	1	1	100.00
		chip_tap_straps_rma	1.478m	2.427ms	1	1	100.00
		chip_tap_straps_prod	1.657m	2.007ms	1	1	100.00
		chip_rv_dm_lc_disabled	2.959m	9.235ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.571m	4.119ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.316m	3.853ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.562m	3.296ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	2.085m	3.799ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	18.798m	22.155ms	1	1	100.00
		chip_rv_dm_lc_disabled	2.959m	9.235ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.088h	47.531ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.092h	50.452ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	9.893m	11.002ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.074h	46.105ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	18.798m	22.155ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.303m	2.491ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.023m	2.244ms	1	1	100.00
		rom_volatile_raw_unlock	1.016m	2.279ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	56.691m	17.274ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.302m	18.347ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	10.143m	5.504ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	10.143m	5.504ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	10.143m	5.504ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	4.278m	3.195ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	8.436m	12.865ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	20.671m	21.250ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.278m	3.195ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.936m	11.940ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.842m	4.526ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.516m	2.903ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	20.671m	21.250ms	1	1	100.00
		chip_sw_otbn_mem_scramble	4.278m	3.195ms	1	1	100.00
		chip_sw_keymgr_key_derivation	24.936m	11.940ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	4.842m	4.526ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.516m	2.903ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	8.436m	12.865ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.255m	4.715ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.719m	2.812ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.698m	3.601ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	9.626m	6.736ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	10.195m	6.959ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	9.976m	7.452ms	0	1	0.00
		chip_sw_lc_ctrl_transition	8.436m	12.865ms	1	1	100.00
		chip_prim_tl_access	3.698m	9.494ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	3.698m	9.494ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	19.332m	8.953ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	6.312m	10.105ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	20.496m	25.755ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.961m	7.320ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.362m	7.262ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.748m	7.958ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	14.263m	22.732ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	14.515m	14.429ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	8.400m	7.565ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	10.615m	8.771ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.605m	5.402ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	6.312m	10.105ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	3.183m	3.602ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	4.362m	5.764ms	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	4.904m	7.161ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	3.614m	4.909ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.458m	20.694ms	0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.155m	6.699ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	14.494m	11.070ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	23.658m	24.468ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	2.544m	2.492ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	5.914m	5.089ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	5.127m	8.853ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	5.127m	8.853ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	14.494m	11.070ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	25.458m	20.694ms	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	5.605m	5.402ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.580m	5.830ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.884m	4.300ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.959m	5.313ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	3.235m	4.614ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.567m	10.548ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.699m	2.697ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	5.914m	5.089ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	19.587m	8.949ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.142m	4.990ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	8.236m	4.811ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	2.867m	2.941ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.516m	2.903ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.959m	5.313ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.959m	5.313ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	9.603m	8.770ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	14.742m	12.764ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.884m	4.300ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.281m	4.119ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	6.245m	6.716ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.478m	2.427ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	2.959m	9.235ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.033m	5.217ms	1	1	100.00
		chip_plic_all_irqs_10	4.496m	3.396ms	1	1	100.00
		chip_plic_all_irqs_20	6.942m	5.093ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.963m	3.097ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.620m	2.903ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	42.758m	14.529ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	6.712m	5.497ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.410m	3.509ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.849m	3.361ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.198m	2.888ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	4.842m	4.526ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	5.704m	4.696ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	7.481m	8.227ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	6.947m	7.138ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	6.803m	7.134ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	5.914m	5.089ms	1	1	100.00
		chip_sw_data_integrity_escalation	7.176m	5.219ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	9.155m	6.699ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	19.661m	22.896ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.800m	3.157ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	2.834m	3.278ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.387m	4.048ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	19.661m	22.896ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	19.661m	22.896ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	14.261m	11.600ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	14.261m	11.600ms	0	1	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	4.264m	5.968ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	53.746m	34.761ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.006m	2.767ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	2.624m	2.828ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.456m	3.679ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	5.118m	3.328ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	17.368m	7.637ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.373h	31.463ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	29.822m	12.836ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.614m	2.864ms	1	1	100.00
V2		TOTAL			231	275	84.00
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.802m	3.221ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.087m	3.201ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	2.672h	71.739ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	8.591m	4.009ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.556m	11.606ms	1	1	100.00
		rom_e2e_jtag_debug_dev	19.022m	11.026ms	1	1	100.00
		rom_e2e_jtag_debug_rma	18.477m	12.238ms	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	2.737m	3.185ms	1	1	100.00
		rom_e2e_jtag_inject_dev	2.999m	3.475ms	1	1	100.00
		rom_e2e_jtag_inject_rma	4.051m	4.413ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.423s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.203m	5.769ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.296m	2.461ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	11.240m	4.467ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	11.822m	6.934ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.079m	2.654ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	10.902m	5.285ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.907m	2.477ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	3.567m	3.508ms	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	5.217m	6.580ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.441m	5.362ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	14.494m	11.070ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.556m	11.606ms	1	1	100.00
		rom_e2e_jtag_debug_dev	19.022m	11.026ms	1	1	100.00
		rom_e2e_jtag_debug_rma	18.477m	12.238ms	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.003m	4.722ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	5.914m	5.089ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.465h	38.487ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.465h	38.487ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.611m	3.612ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	6.988m	4.580ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	52.311m	18.835ms	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	2.399m	2.758ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.019m	4.670ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	34.236m	30.327ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.653m	2.857ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	3.068m	3.171ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.003m	4.179ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.527s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	3.258m	2.944ms	1	1	100.00
		TOTAL			277	326	84.97

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.94200770355591727816528998402936291367764768634537947173296700112627679808567
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.114309589274801025856364039124307583906120009518645226219543362469479484483398
    Line 507, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.99261797671617843357422933373715077911320329591570284727614314083004533222139
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2851730913083902956635543186783434318710428558531824630854966708276225647237
    Line 508, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.64441995878762012305528800469129737835819669203998685816040538441462593226498
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.46121294890722509493392618265042080842342922747395717426245252891188230803660
    Line 514, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.47619565290256445938736194267003168248294776020916365877816777046446720122180
    Line 510, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.31653537175318822498556034903153590916744126418916188174993068273276610110058
    Line 473, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.95418761215739394732060495532193124100304945164080397909425295361942325423850
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.63055002174340252313924707901376634193787453033870291310988315351378469364146
    Line 499, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.11327482895752809360406147064748248689166148644001172390548627448940307862551
    Line 468, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.28689375454709116601962419015393921117624496314953159094346985373933226465226
    Line 450, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.9087605580311795532111462779265127342740122692856896987021509946681928664937
    Line 490, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.86485440074110095342181768818240289308656490643142543762647031883490860193404
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3507.934438 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3507.934438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.99137435540898676369201116342546328477442738852993197891259305614254272407944
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2208.544572 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2208.544572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(pend_req[h2d.a_source].pend == *)' has 2 failures:

Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.

0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.79326555852651028993116800238340215315062268449819159407839799519145797808498
Line 470, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 15286042176ps failed at 15286042176ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 15286125504ps failed at 15286125504ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

Test rom_e2e_static_critical has 1 failures.

0.rom_e2e_static_critical.34308429428062896067973014031426029998317674093978805275540714301447626786604
Line 411, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_static_critical/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2392160955ps failed at 2392160955ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 2392374635ps failed at 2392374635ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

Offending '(rstreqs[*] && (reset_cause == HwReq))' has 2 failures:
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.112690535518705824853048831247193019804079960102474482081403258694139470731072
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 7261.620000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7261.620000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.80050838332332032356262554044946950988852148543360877358149374121964372634978
    Line 399, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 5764.022000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 5764.022000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.45598483931400066479220381334422114405561901204263742695725760579646793077815
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.148s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.27490422615881312468776793440775349754391704400732001383690538716633444248201
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.155s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.72152995368997384710369887890445698284185282578356303787200404042983144392638
    Line 524, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.16251696960136515764058158776529167709319573524432917223951865602473937706181
    Line 531, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.16234582041474272581142474400969950128038302465429654819300645913551001497694
    Line 554, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.74150268108882271818617734525363829084283030426211961033433587021018384142882
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.25778575001217246938047316464682487495033157139394227586013257553308520346401
    Line 402, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3508.573675 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3508.573675 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.13042697031885378729516003316645830465140066808208159174881723576523048909145
    Line 417, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 7452.258160 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 7452.258160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.50897993010901992615014922408775416878729375078843523562719385829052619580624
    Line 447, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 30326.814633 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 30326.814633 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@118330) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.63416227292132401917048894575269533819861400433691424936889272954478644431779
Line 417, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 5313.149250 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@118330) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5313.149250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor has 1 failures:
- Test chip_sw_sysrst_ctrl_ec_rst_l has 1 failures.
  - 0.chip_sw_sysrst_ctrl_ec_rst_l.32917572791693171210424404439022457752452786036813504130861458063517677366825
    Line 410, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_ec_rst_l/latest/run.log
```
  UVM_ERROR @ 11600.125068 us: (sw_logger_if.sv:526) [sysrst_ctrl_ec_rst_l_test_sim_dv(sw/device/tests/sim_dv/sysrst_ctrl_ec_rst_l_test.c:200)] CHECK-fail: rstmgr_reset_info == kDifRstmgrResetInfoPor
  UVM_INFO @ 11600.125068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.36742370641394846173468762054463818967575282808617418150204631613426722525259
    Line 416, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34760.977911 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34760.977911 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.95200304863767958461087663471214585033728196748187836720209787387349904476815
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 3001.465105 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
  UVM_INFO @ 3001.465105 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.106508885411634865220943211486186891124308119237726337012988658918893595397891
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2938.386696 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2938.386696 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.56129820147065253585180493141908125621500586311369421675086376469568592263922
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.25105175434560344598037972103903874130624171047742327966200406670110639381353
    Line 401, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 3093.864900 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 3093.864900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@366932) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.114015509703535136387475119944231184844512613905152139485972108022565175842023
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 5213.010301 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@366932) { a_addr: 'h105d8  a_data: 'h34d86886  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h1bae5  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5213.010301 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.34589733018299004661935307560909828535178128717928376959458243420106588710106
    Line 242, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 9235.462550 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x106f8 read out mismatch
  UVM_INFO @ 9235.462550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.86842727619617346512090380766885078121519527474704166959105525409041594577918
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3518.253500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3518.253500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.42189434871010910927912293763793413533615391771784728247477924482755095388107
    Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2896.985000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2896.985000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.10468325043259941422505885211644599497380697793172977726880277149391122136786
    Line 425, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 19807.382118 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 19807.382118 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.93078215530438858336033375372721683016937917338694093752946271081728387227590
    Line 446, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4009.457224 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 4009.457224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.54216901598291139399286642545106665833696372593003564672278296832850929172140
    Line 462, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.21515748687117027519998338344469325233407825039595520639404312977880078203323
    Line 461, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```