ADC_CTRL Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: e383c23

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	14.720s	6.159ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.220s	705.789us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	1.290s	375.386us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	16.930s	26.627ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.360s	976.890us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.790s	455.622us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	1.290s	375.386us	1	1	100.00
		adc_ctrl_csr_aliasing	5.360s	976.890us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	8.930m	337.719ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	14.476m	486.292ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.510m	334.098ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	12.379m	485.813ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	3.104m	660.312ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	1.892m	200.267ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	1.667m	211.953ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	2.007m	340.292ms	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	6.260s	3.212ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	17.890s	34.637ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	3.805m	125.193ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	2.344m	180.359ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.520s	323.730us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.760s	516.042us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	1.530s	638.380us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	1.530s	638.380us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.220s	705.789us	1	1	100.00
		adc_ctrl_csr_rw	1.290s	375.386us	1	1	100.00
		adc_ctrl_csr_aliasing	5.360s	976.890us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.140s	2.192ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.220s	705.789us	1	1	100.00
		adc_ctrl_csr_rw	1.290s	375.386us	1	1	100.00
		adc_ctrl_csr_aliasing	5.360s	976.890us	1	1	100.00
		adc_ctrl_same_csr_outstanding	4.140s	2.192ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	5.420s	4.557ms	1	1	100.00
		adc_ctrl_tl_intg_err	4.580s	8.296ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	4.580s	8.296ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	7.140s	3.201ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.105745104771324880407401334448887836573675888787140427554670707522003459042046
      Line 182, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 340291830914 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 340291830914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---