EDN Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: e383c23

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.860s	15.061us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.970s	21.694us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.870s	26.206us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.270s	115.786us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.160s	72.024us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.350s	39.248us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.870s	26.206us	1	1	100.00
		edn_csr_aliasing	1.160s	72.024us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	0.990s	75.850us	1	1	100.00
V2	csrng_commands	edn_genbits	0.990s	75.850us	1	1	100.00
V2	genbits	edn_genbits	0.990s	75.850us	1	1	100.00
V2	interrupts	edn_intr	0.870s	21.264us	1	1	100.00
V2	alerts	edn_alert	1.080s	63.362us	1	1	100.00
V2	errs	edn_err	0.960s	24.921us	1	1	100.00
V2	disable	edn_disable	0.760s	17.843us	1	1	100.00
		edn_disable_auto_req_mode	1.020s	134.051us	1	1	100.00
V2	stress_all	edn_stress_all	2.350s	258.028us	1	1	100.00
V2	intr_test	edn_intr_test	0.830s	23.463us	1	1	100.00
V2	alert_test	edn_alert_test	0.870s	37.761us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.900s	120.371us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.900s	120.371us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.970s	21.694us	1	1	100.00
		edn_csr_rw	0.870s	26.206us	1	1	100.00
		edn_csr_aliasing	1.160s	72.024us	1	1	100.00
		edn_same_csr_outstanding	1.010s	50.954us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.970s	21.694us	1	1	100.00
		edn_csr_rw	0.870s	26.206us	1	1	100.00
		edn_csr_aliasing	1.160s	72.024us	1	1	100.00
		edn_same_csr_outstanding	1.010s	50.954us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	5.520s	466.008us	1	1	100.00
		edn_tl_intg_err	1.780s	76.314us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.770s	43.605us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.080s	63.362us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.520s	466.008us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.520s	466.008us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.520s	466.008us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.520s	466.008us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.080s	63.362us	1	1	100.00
		edn_sec_cm	5.520s	466.008us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.080s	63.362us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.780s	76.314us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	39.390s	6.199ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00