HMAC Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: e383c23

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 11.650s 347.411us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.890s 22.291us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.900s 29.154us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.470s 8.725ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.970s 2.178ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.810s 164.241us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.900s 29.154us 1 1 100.00
hmac_csr_aliasing 5.970s 2.178ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 45.720s 4.407ms 1 1 100.00
V2 back_pressure hmac_back_pressure 13.260s 3.822ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.100s 342.182us 1 1 100.00
hmac_test_sha384_vectors 18.870s 3.103ms 1 1 100.00
hmac_test_sha512_vectors 20.510s 239.571us 1 1 100.00
hmac_test_hmac256_vectors 6.250s 209.956us 1 1 100.00
hmac_test_hmac384_vectors 7.630s 245.377us 1 1 100.00
hmac_test_hmac512_vectors 11.780s 1.517ms 1 1 100.00
V2 burst_wr hmac_burst_wr 10.120s 3.776ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 13.148m 25.123ms 1 1 100.00
V2 error hmac_error 18.080s 816.648us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 24.240s 1.782ms 1 1 100.00
V2 save_and_restore hmac_smoke 11.650s 347.411us 1 1 100.00
hmac_long_msg 45.720s 4.407ms 1 1 100.00
hmac_back_pressure 13.260s 3.822ms 1 1 100.00
hmac_datapath_stress 13.148m 25.123ms 1 1 100.00
hmac_burst_wr 10.120s 3.776ms 1 1 100.00
hmac_stress_all 19.290s 840.176us 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 11.650s 347.411us 1 1 100.00
hmac_long_msg 45.720s 4.407ms 1 1 100.00
hmac_back_pressure 13.260s 3.822ms 1 1 100.00
hmac_datapath_stress 13.148m 25.123ms 1 1 100.00
hmac_wipe_secret 24.240s 1.782ms 1 1 100.00
hmac_test_sha256_vectors 8.100s 342.182us 1 1 100.00
hmac_test_sha384_vectors 18.870s 3.103ms 1 1 100.00
hmac_test_sha512_vectors 20.510s 239.571us 1 1 100.00
hmac_test_hmac256_vectors 6.250s 209.956us 1 1 100.00
hmac_test_hmac384_vectors 7.630s 245.377us 1 1 100.00
hmac_test_hmac512_vectors 11.780s 1.517ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 11.650s 347.411us 1 1 100.00
hmac_long_msg 45.720s 4.407ms 1 1 100.00
hmac_back_pressure 13.260s 3.822ms 1 1 100.00
hmac_datapath_stress 13.148m 25.123ms 1 1 100.00
hmac_burst_wr 10.120s 3.776ms 1 1 100.00
hmac_error 18.080s 816.648us 1 1 100.00
hmac_wipe_secret 24.240s 1.782ms 1 1 100.00
hmac_test_sha256_vectors 8.100s 342.182us 1 1 100.00
hmac_test_sha384_vectors 18.870s 3.103ms 1 1 100.00
hmac_test_sha512_vectors 20.510s 239.571us 1 1 100.00
hmac_test_hmac256_vectors 6.250s 209.956us 1 1 100.00
hmac_test_hmac384_vectors 7.630s 245.377us 1 1 100.00
hmac_test_hmac512_vectors 11.780s 1.517ms 1 1 100.00
hmac_stress_all 19.290s 840.176us 1 1 100.00
V2 stress_all hmac_stress_all 19.290s 840.176us 1 1 100.00
V2 alert_test hmac_alert_test 0.600s 25.814us 1 1 100.00
V2 intr_test hmac_intr_test 0.620s 19.528us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 1.800s 375.659us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 1.800s 375.659us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.890s 22.291us 1 1 100.00
hmac_csr_rw 0.900s 29.154us 1 1 100.00
hmac_csr_aliasing 5.970s 2.178ms 1 1 100.00
hmac_same_csr_outstanding 1.620s 50.974us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.890s 22.291us 1 1 100.00
hmac_csr_rw 0.900s 29.154us 1 1 100.00
hmac_csr_aliasing 5.970s 2.178ms 1 1 100.00
hmac_same_csr_outstanding 1.620s 50.974us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.340s 516.737us 1 1 100.00
hmac_tl_intg_err 2.210s 246.635us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.210s 246.635us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 11.650s 347.411us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.060s 618.008us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 31.010s 4.299ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.930s 64.747us 1 1 100.00
TOTAL 28 28 100.00