e383c23| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | host_smoke | i2c_host_smoke | 14.200s | 1.696ms | 1 | 1 | 100.00 |
| V1 | target_smoke | i2c_target_smoke | 8.110s | 5.032ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | i2c_csr_hw_reset | 0.850s | 59.836us | 1 | 1 | 100.00 |
| V1 | csr_rw | i2c_csr_rw | 0.970s | 23.170us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | i2c_csr_bit_bash | 3.840s | 2.045ms | 1 | 1 | 100.00 |
| V1 | csr_aliasing | i2c_csr_aliasing | 1.410s | 134.334us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | i2c_csr_mem_rw_with_rand_reset | 0.910s | 36.660us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | i2c_csr_rw | 0.970s | 23.170us | 1 | 1 | 100.00 |
| i2c_csr_aliasing | 1.410s | 134.334us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 7 | 7 | 100.00 | |||
| V2 | host_error_intr | i2c_host_error_intr | 3.670s | 111.172us | 0 | 1 | 0.00 |
| V2 | host_stress_all | i2c_host_stress_all | 9.380s | 839.191us | 0 | 1 | 0.00 |
| V2 | host_maxperf | i2c_host_perf | 1.270m | 5.091ms | 1 | 1 | 100.00 |
| V2 | host_override | i2c_host_override | 0.960s | 38.174us | 1 | 1 | 100.00 |
| V2 | host_fifo_watermark | i2c_host_fifo_watermark | 50.160s | 5.323ms | 1 | 1 | 100.00 |
| V2 | host_fifo_overflow | i2c_host_fifo_overflow | 37.970s | 2.188ms | 1 | 1 | 100.00 |
| V2 | host_fifo_reset | i2c_host_fifo_reset_fmt | 1.580s | 180.418us | 1 | 1 | 100.00 |
| i2c_host_fifo_fmt_empty | 14.130s | 1.709ms | 1 | 1 | 100.00 | ||
| i2c_host_fifo_reset_rx | 4.250s | 1.917ms | 1 | 1 | 100.00 | ||
| V2 | host_fifo_full | i2c_host_fifo_full | 59.610s | 12.809ms | 1 | 1 | 100.00 |
| V2 | host_timeout | i2c_host_stretch_timeout | 21.960s | 3.008ms | 1 | 1 | 100.00 |
| V2 | i2c_host_mode_toggle | i2c_host_mode_toggle | 0.790s | 63.796us | 0 | 1 | 0.00 |
| V2 | target_glitch | i2c_target_glitch | 2.250s | 536.509us | 0 | 1 | 0.00 |
| V2 | target_stress_all | i2c_target_stress_all | 27.080s | 29.418ms | 1 | 1 | 100.00 |
| V2 | target_maxperf | i2c_target_perf | 3.760s | 673.640us | 1 | 1 | 100.00 |
| V2 | target_fifo_empty | i2c_target_stress_rd | 19.600s | 1.363ms | 1 | 1 | 100.00 |
| i2c_target_intr_smoke | 4.000s | 3.777ms | 1 | 1 | 100.00 | ||
| V2 | target_fifo_reset | i2c_target_fifo_reset_acq | 1.200s | 175.802us | 1 | 1 | 100.00 |
| i2c_target_fifo_reset_tx | 1.180s | 646.981us | 1 | 1 | 100.00 | ||
| V2 | target_fifo_full | i2c_target_stress_wr | 13.160s | 23.789ms | 1 | 1 | 100.00 |
| i2c_target_stress_rd | 19.600s | 1.363ms | 1 | 1 | 100.00 | ||
| i2c_target_intr_stress_wr | 4.550s | 4.067ms | 1 | 1 | 100.00 | ||
| V2 | target_timeout | i2c_target_timeout | 5.000s | 5.565ms | 1 | 1 | 100.00 |
| V2 | target_clock_stretch | i2c_target_stretch | 1.730s | 635.035us | 1 | 1 | 100.00 |
| V2 | bad_address | i2c_target_bad_addr | 4.770s | 2.701ms | 1 | 1 | 100.00 |
| V2 | target_mode_glitch | i2c_target_hrst | 1.460s | 382.831us | 1 | 1 | 100.00 |
| V2 | target_fifo_watermark | i2c_target_fifo_watermarks_acq | 2.010s | 567.139us | 1 | 1 | 100.00 |
| i2c_target_fifo_watermarks_tx | 1.530s | 164.256us | 1 | 1 | 100.00 | ||
| V2 | host_mode_config_perf | i2c_host_perf | 1.270m | 5.091ms | 1 | 1 | 100.00 |
| i2c_host_perf_precise | 4.940s | 888.097us | 1 | 1 | 100.00 | ||
| V2 | host_mode_clock_stretching | i2c_host_stretch_timeout | 21.960s | 3.008ms | 1 | 1 | 100.00 |
| V2 | target_mode_tx_stretch_ctrl | i2c_target_tx_stretch_ctrl | 1.430s | 59.634us | 1 | 1 | 100.00 |
| V2 | target_mode_nack_generation | i2c_target_nack_acqfull | 1.830s | 994.531us | 1 | 1 | 100.00 |
| i2c_target_nack_acqfull_addr | 1.590s | 6.799ms | 1 | 1 | 100.00 | ||
| i2c_target_nack_txstretch | 1.330s | 145.957us | 1 | 1 | 100.00 | ||
| V2 | host_mode_halt_on_nak | i2c_host_may_nack | 3.170s | 1.233ms | 1 | 1 | 100.00 |
| V2 | target_mode_smbus_maxlen | i2c_target_smbus_maxlen | 2.320s | 2.042ms | 1 | 1 | 100.00 |
| V2 | alert_test | i2c_alert_test | 0.700s | 23.301us | 1 | 1 | 100.00 |
| V2 | intr_test | i2c_intr_test | 0.760s | 41.572us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | i2c_tl_errors | 1.840s | 44.469us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | i2c_tl_errors | 1.840s | 44.469us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | i2c_csr_hw_reset | 0.850s | 59.836us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.970s | 23.170us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 1.410s | 134.334us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 1.180s | 149.869us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | i2c_csr_hw_reset | 0.850s | 59.836us | 1 | 1 | 100.00 |
| i2c_csr_rw | 0.970s | 23.170us | 1 | 1 | 100.00 | ||
| i2c_csr_aliasing | 1.410s | 134.334us | 1 | 1 | 100.00 | ||
| i2c_same_csr_outstanding | 1.180s | 149.869us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 34 | 38 | 89.47 | |||
| V2S | tl_intg_err | i2c_tl_intg_err | 2.010s | 280.250us | 1 | 1 | 100.00 |
| i2c_sec_cm | 1.100s | 67.202us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | i2c_tl_intg_err | 2.010s | 280.250us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | host_stress_all_with_rand_reset | i2c_host_stress_all_with_rand_reset | 31.190s | 764.091us | 0 | 1 | 0.00 |
| V3 | target_error_intr | i2c_target_unexp_stop | 1.370s | 997.478us | 0 | 1 | 0.00 |
| V3 | target_stress_all_with_rand_reset | i2c_target_stress_all_with_rand_reset | 4.470s | 1.455ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 43 | 50 | 86.00 |
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:
Test i2c_host_error_intr has 1 failures.
0.i2c_host_error_intr.56913568961743093555524904097586414330357857625309111969981539646190025519565
Line 123, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log
UVM_ERROR @ 111172339 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 111172339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_host_stress_all has 1 failures.
0.i2c_host_stress_all.34718545961004034262206865716685065782313433960457760398201189191796433184551
Line 94, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
UVM_ERROR @ 839191486 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 839191486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
Test i2c_host_stress_all_with_rand_reset has 1 failures.
0.i2c_host_stress_all_with_rand_reset.24792113504639089323276178910483488056261068621580896851981877158050064334979
Line 115, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 764091098 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 764091098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test i2c_target_stress_all_with_rand_reset has 1 failures.
0.i2c_target_stress_all_with_rand_reset.115183221659786607306345827221539560358846325217136477766856511503941777484932
Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1454818097 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1454818097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
0.i2c_target_glitch.114094144596278798881841827713486153563736232060804655716503021074685230891001
Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
UVM_ERROR @ 536509344 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 536509344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
0.i2c_target_unexp_stop.109037389251804594013316625549531284841192095663629290712895582674388552659325
Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
UVM_ERROR @ 997478461 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 62 [0x3e])
UVM_INFO @ 997478461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
0.i2c_host_mode_toggle.24254058144532716066870478975651089073428473467033510565486075359365994137664
Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log
UVM_FATAL @ 63796070 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=0xaf3f8994, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
UVM_INFO @ 63796070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---