KEYMGR Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: e383c23

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	1.780s	53.739us	1	1	100.00
V1	random	keymgr_random	12.210s	1.501ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	0.980s	34.132us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	0.720s	40.710us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.770s	1.045ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.160s	735.027us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.190s	424.560us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	0.720s	40.710us	1	1	100.00
		keymgr_csr_aliasing	6.160s	735.027us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	3.570s	107.173us	1	1	100.00
V2	sideload	keymgr_sideload	1.810s	43.515us	1	1	100.00
		keymgr_sideload_kmac	17.250s	3.951ms	1	1	100.00
		keymgr_sideload_aes	3.150s	281.554us	1	1	100.00
		keymgr_sideload_otbn	31.450s	8.150ms	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.060s	73.502us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	2.050s	224.894us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	4.070s	134.785us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.270s	98.272us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.630s	156.434us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	1.840s	192.169us	1	1	100.00
V2	stress_all	keymgr_stress_all	12.490s	1.249ms	1	1	100.00
V2	intr_test	keymgr_intr_test	0.750s	44.860us	1	1	100.00
V2	alert_test	keymgr_alert_test	0.990s	17.634us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	1.740s	83.759us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	1.740s	83.759us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	0.980s	34.132us	1	1	100.00
		keymgr_csr_rw	0.720s	40.710us	1	1	100.00
		keymgr_csr_aliasing	6.160s	735.027us	1	1	100.00
		keymgr_same_csr_outstanding	1.690s	51.422us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	0.980s	34.132us	1	1	100.00
		keymgr_csr_rw	0.720s	40.710us	1	1	100.00
		keymgr_csr_aliasing	6.160s	735.027us	1	1	100.00
		keymgr_same_csr_outstanding	1.690s	51.422us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	10.810s	1.570ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	10.810s	1.570ms	1	1	100.00
		keymgr_tl_intg_err	5.250s	554.650us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	3.500s	200.145us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	3.500s	200.145us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	3.500s	200.145us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	3.500s	200.145us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.470s	204.845us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	10.810s	1.570ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	10.810s	1.570ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	5.250s	554.650us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	3.500s	200.145us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.570s	107.173us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	12.210s	1.501ms	1	1	100.00
		keymgr_csr_rw	0.720s	40.710us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	12.210s	1.501ms	1	1	100.00
		keymgr_csr_rw	0.720s	40.710us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	12.210s	1.501ms	1	1	100.00
		keymgr_csr_rw	0.720s	40.710us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	2.050s	224.894us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.630s	156.434us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.630s	156.434us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	12.210s	1.501ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	1.800s	38.226us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	10.810s	1.570ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	10.810s	1.570ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	10.810s	1.570ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	2.290s	126.224us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	2.050s	224.894us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	10.810s	1.570ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	10.810s	1.570ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	10.810s	1.570ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	2.290s	126.224us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	2.290s	126.224us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	10.810s	1.570ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	2.290s	126.224us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	10.810s	1.570ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	2.290s	126.224us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	2.240s	717.259us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	30	96.67

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1229) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.11281351094140255627857407760315304784277487131939582534597407218887959937368
      Line 238, in log /nightly/current_run/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 717258570 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 717258570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---