RV_DM/USE_JTAG_INTERFACE Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: `e383c23`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	1.860s	1.641ms	1	1	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	1.830s	1.194ms	1	1	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	1.180s	432.322us	1	1	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	25.780s	15.042ms	1	1	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	3.070s	2.067ms	1	1	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	1.790s	1.184ms	1	1	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	4.870s	1.995ms	1	1	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	25.680s	42.106ms	1	1	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	56.550s	50.716ms	1	1	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.180s	254.601us	1	1	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	1.190s	271.436us	1	1	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.230s	192.721us	1	1	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	0.980s	334.736us	1	1	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.150s	97.128us	1	1	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	0.940s	158.839us	1	1	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.130s	202.009us	1	1	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	2.010s	689.228us	1	1	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	1.180s	254.601us	1	1	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	0.850s	237.097us	1	1	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.110s	443.968us	1	1	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	1.230s	192.721us	1	1	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.020s	130.108us	1	1	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	1.570s	824.351us	1	1	100.00
V1	csr_rw	rv_dm_csr_rw	2.150s	99.686us	1	1	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	44.390s	9.977ms	1	1	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	21.650s	4.300ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	0.800s	64.777us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	21.650s	4.300ms	1	1	100.00
		rv_dm_csr_rw	2.150s	99.686us	1	1	100.00
V1	mem_walk	rv_dm_mem_walk	0.950s	61.853us	1	1	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.000s	81.914us	1	1	100.00
V1		TOTAL			26	27	96.30
V2	idcode	rv_dm_smoke	1.860s	1.641ms	1	1	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.000s	111.519us	1	1	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.570s	556.276us	1	1	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	0.970s	570.736us	1	1	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	1.170s	528.222us	1	1	100.00
V2	sba	rv_dm_sba_tl_access	8.734m	300.000ms	0	1	0.00
		rv_dm_delayed_resp_sba_tl_access	4.837m	300.000ms	0	1	0.00
V2	bad_sba	rv_dm_bad_sba_tl_access	9.160m	300.000ms	0	1	0.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	9.551m	300.000ms	0	1	0.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.170s	389.862us	1	1	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	1.410s	988.343us	1	1	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	1.780s	584.015us	1	1	100.00
V2	hart_unavail	rv_dm_hart_unavail	1.230s	335.067us	1	1	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	18.530s	9.694ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.330s	59.670us	0	1	0.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.940s	159.536us	1	1	100.00
V2	stress_all	rv_dm_stress_all	2.370s	2.856ms	1	1	100.00
V2	alert_test	rv_dm_alert_test	0.670s	152.671us	1	1	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	2.080s	76.688us	1	1	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	2.080s	76.688us	1	1	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	21.650s	4.300ms	1	1	100.00
		rv_dm_csr_hw_reset	1.570s	824.351us	1	1	100.00
		rv_dm_csr_rw	2.150s	99.686us	1	1	100.00
		rv_dm_same_csr_outstanding	5.240s	651.517us	1	1	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	21.650s	4.300ms	1	1	100.00
		rv_dm_csr_hw_reset	1.570s	824.351us	1	1	100.00
		rv_dm_csr_rw	2.150s	99.686us	1	1	100.00
		rv_dm_same_csr_outstanding	5.240s	651.517us	1	1	100.00
V2		TOTAL			14	19	73.68
V2S	tl_intg_err	rv_dm_sec_cm	1.150s	773.787us	1	1	100.00
		rv_dm_tl_intg_err	14.740s	4.878ms	1	1	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	14.740s	4.878ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	1.410s	988.343us	1	1	100.00
		rv_dm_debug_disabled	0.820s	66.374us	1	1	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	1.410s	988.343us	1	1	100.00
		rv_dm_debug_disabled	0.820s	66.374us	1	1	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	1.860s	1.641ms	1	1	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	1.020s	439.187us	1	1	100.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.780s	115.305us	1	1	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	0.780s	115.305us	1	1	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	1.020s	439.187us	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	1.360s	74.172us	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	rv_dm_scanmode	0.770s	18.570us	1	1	100.00
		TOTAL			46	53	86.79

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
- Test rv_dm_sba_tl_access has 1 failures.
  - 0.rv_dm_sba_tl_access.5760845160928709336133714657897706756787709533709736552855799468929317911625
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
  - 0.rv_dm_delayed_resp_sba_tl_access.89552661692198085383057197193722759508193838901508862974579451902208691929233
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_bad_sba_tl_access has 1 failures.
  - 0.rv_dm_bad_sba_tl_access.74361062194535068325325282759284499530573450611675357622103742067513643712179
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rv_dm_autoincr_sba_tl_access has 1 failures.
  - 0.rv_dm_autoincr_sba_tl_access.74523990785165704035674686176752559153774595601819266610715318177959860286419
    Line 83, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
```
  UVM_FATAL @ 300000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 300000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@20940) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_tap_fsm_rand_reset has 1 failures.

0.rv_dm_tap_fsm_rand_reset.61720659780424373229480800704261078759232560100076538382059740349619227409631
Line 84, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log

  UVM_ERROR @  59669964 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@20940) { a_addr: 'h1206d45c  a_data: 'h65b8fd8e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hae  a_opcode: 'h4  a_user: 'h18505  d_param: 'h0  d_source: 'hae  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  59669964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@18844) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_stress_all_with_rand_reset has 1 failures.

0.rv_dm_stress_all_with_rand_reset.41442683737963085652192736963847517076704602862713742817168837654959232741163
Line 82, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  74172044 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@18844) { a_addr: 'h25f6e458  a_data: 'hfc674845  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h4  a_user: 'h1a9b7  d_param: 'h0  d_source: 'h20  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  74172044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@7148) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test rv_dm_csr_mem_rw_with_rand_reset has 1 failures.

0.rv_dm_csr_mem_rw_with_rand_reset.31133197796369099941555820896099433689178852524595934425481247605374087787997
Line 76, in log /nightly/current_run/scratch/master/rv_dm-sim-vcs/0.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  64777171 ps: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface rv_dm_mem_reg_block, TL item: req: (cip_tl_seq_item@7148) { a_addr: 'hb6a01584  a_data: 'h83e9d9d5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h89  a_opcode: 'h4  a_user: 'h1b943  d_param: 'h0  d_source: 'h89  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  64777171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---