e383c23| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0.880s | 118.012us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.660s | 16.899us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.840s | 26.332us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.890s | 831.114us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.690s | 73.761us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 1.350s | 41.426us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.840s | 26.332us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.690s | 73.761us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0.680s | 42.950us | 1 | 1 | 100.00 |
| V2 | disabled | rv_timer_disabled | 0.660s | 1.052ms | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 3.536m | 1.161s | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 3.536m | 1.161s | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 0.790s | 99.549us | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.700s | 32.909us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.780s | 47.577us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.660s | 117.561us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.660s | 117.561us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.660s | 16.899us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.840s | 26.332us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.690s | 73.761us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.580s | 20.891us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.660s | 16.899us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.840s | 26.332us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.690s | 73.761us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.580s | 20.891us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 8 | 8 | 100.00 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.940s | 171.349us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 1.470s | 458.432us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.470s | 458.432us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 0.990s | 212.984us | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.770s | 148.518us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 16.330s | 2.728ms | 0 | 1 | 0.00 |
| V3 | TOTAL | 0 | 3 | 0.00 | |||
| TOTAL | 16 | 19 | 84.21 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:
0.rv_timer_min.7568684179517490934878020049749783561760233205080419248486422318935328025428
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 212984391 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xfb524504) == 0x1
UVM_INFO @ 212984391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.37118545431586968307760283183645587436962434400434783166655193933806183178422
Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 148518074 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 148518074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
0.rv_timer_stress_all_with_rand_reset.88973388331286160699691586790931788069347922294110062036110875205525976162134
Line 233, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2728105315 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 2728105315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---