SPI_DEVICE/1R1W Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: e383c23

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.028m	10.953ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.130s	21.105us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.140s	32.075us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.250s	1.835ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.000s	2.006ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.520s	43.716us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.140s	32.075us	1	1	100.00
		spi_device_csr_aliasing	15.000s	2.006ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.780s	26.762us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.120s	122.594us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.970s	54.620us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.820s	1.747us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.870s	12.800us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.280s	29.283us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.280s	29.283us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.860s	23.408ms	1	1	100.00
		spi_device_tpm_sts_read	1.030s	324.090us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	32.030s	30.074ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	2.260s	178.608us	1	1	100.00
		spi_device_flash_all	1.894m	33.290ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.710s	1.311ms	1	1	100.00
		spi_device_flash_all	1.894m	33.290ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.710s	1.311ms	1	1	100.00
		spi_device_flash_all	1.894m	33.290ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.894m	33.290ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.380s	3.495ms	1	1	100.00
		spi_device_flash_all	1.894m	33.290ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.380s	3.495ms	1	1	100.00
		spi_device_flash_all	1.894m	33.290ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.380s	3.495ms	1	1	100.00
		spi_device_flash_all	1.894m	33.290ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.380s	3.495ms	1	1	100.00
		spi_device_flash_all	1.894m	33.290ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.380s	3.495ms	1	1	100.00
		spi_device_flash_all	1.894m	33.290ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.630s	549.228us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	9.150s	6.255ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	9.150s	6.255ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	9.150s	6.255ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.320s	895.764us	1	1	100.00
		spi_device_read_buffer_direct	10.750s	2.717ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	9.150s	6.255ms	1	1	100.00
		spi_device_flash_all	1.894m	33.290ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.894m	33.290ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.894m	33.290ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.230s	96.689us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.230s	96.689us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.028m	10.953ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.643m	13.614ms	1	1	100.00
V2	stress_all	spi_device_stress_all	48.970s	11.398ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.800s	20.158us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.790s	75.221us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.280s	406.963us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.280s	406.963us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.130s	21.105us	1	1	100.00
		spi_device_csr_rw	1.140s	32.075us	1	1	100.00
		spi_device_csr_aliasing	15.000s	2.006ms	1	1	100.00
		spi_device_same_csr_outstanding	1.920s	76.987us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.130s	21.105us	1	1	100.00
		spi_device_csr_rw	1.140s	32.075us	1	1	100.00
		spi_device_csr_aliasing	15.000s	2.006ms	1	1	100.00
		spi_device_same_csr_outstanding	1.920s	76.987us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.040s	159.669us	1	1	100.00
		spi_device_tl_intg_err	9.130s	205.557us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	9.130s	205.557us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	55.360s	5.177ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.1495370297307317115683607164915482082237628780339448852026771812998693443081
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1146932 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[28])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1146932 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1146932 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[924])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.11714484282089873676138284414957679229721635523866911879375218362957153546424
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @  10492463 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x66b2e6 [11001101011001011100110] vs 0x0 [0])
        UVM_ERROR @  10555463 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4a4c14 [10010100100110000010100] vs 0x0 [0])
        UVM_ERROR @  10600463 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x774e49 [11101110100111001001001] vs 0x0 [0])
        UVM_ERROR @  10655463 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8996e0 [100010011001011011100000] vs 0x0 [0])
        UVM_ERROR @  10735463 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3abfd7 [1110101011111111010111] vs 0x0 [0])