SPI_DEVICE/2P Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: e383c23

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.788m	242.814ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.160s	182.491us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.400s	143.716us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	24.520s	7.489ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.410s	611.504us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	1.980s	73.898us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.400s	143.716us	1	1	100.00
		spi_device_csr_aliasing	10.410s	611.504us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.920s	13.381us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.640s	47.658us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.860s	78.541us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.050s	17.204us	1	1	100.00
V2	mem_cfg	spi_device_ram_cfg	0.810s	16.385us	1	1	100.00
V2	tpm_read	spi_device_tpm_rw	1.100s	73.690us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.100s	73.690us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	10.130s	23.463ms	1	1	100.00
		spi_device_tpm_sts_read	0.860s	17.016us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	13.180s	14.944ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	1.610s	34.929us	1	1	100.00
		spi_device_flash_all	0.740s	52.593us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.790s	1.230ms	1	1	100.00
		spi_device_flash_all	0.740s	52.593us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.790s	1.230ms	1	1	100.00
		spi_device_flash_all	0.740s	52.593us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	0.740s	52.593us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	4.630s	2.515ms	1	1	100.00
		spi_device_flash_all	0.740s	52.593us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	4.630s	2.515ms	1	1	100.00
		spi_device_flash_all	0.740s	52.593us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	4.630s	2.515ms	1	1	100.00
		spi_device_flash_all	0.740s	52.593us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	4.630s	2.515ms	1	1	100.00
		spi_device_flash_all	0.740s	52.593us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	4.630s	2.515ms	1	1	100.00
		spi_device_flash_all	0.740s	52.593us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	9.170s	3.634ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	37.660s	15.464ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	37.660s	15.464ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	37.660s	15.464ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.520s	2.440ms	1	1	100.00
		spi_device_read_buffer_direct	6.350s	4.377ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	37.660s	15.464ms	1	1	100.00
		spi_device_flash_all	0.740s	52.593us	1	1	100.00
V2	quad_spi	spi_device_flash_all	0.740s	52.593us	1	1	100.00
V2	dual_spi	spi_device_flash_all	0.740s	52.593us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	18.350s	8.062ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	18.350s	8.062ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.788m	242.814ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.590s	1.462ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.741m	8.016ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.860s	43.828us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.860s	19.102us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.720s	226.670us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.720s	226.670us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.160s	182.491us	1	1	100.00
		spi_device_csr_rw	1.400s	143.716us	1	1	100.00
		spi_device_csr_aliasing	10.410s	611.504us	1	1	100.00
		spi_device_same_csr_outstanding	1.470s	27.869us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.160s	182.491us	1	1	100.00
		spi_device_csr_rw	1.400s	143.716us	1	1	100.00
		spi_device_csr_aliasing	10.410s	611.504us	1	1	100.00
		spi_device_same_csr_outstanding	1.470s	27.869us	1	1	100.00
V2		TOTAL			22	22	100.00
V2S	tl_intg_err	spi_device_sec_cm	1.230s	149.549us	1	1	100.00
		spi_device_tl_intg_err	6.590s	366.665us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.590s	366.665us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.859m	23.748ms	1	1	100.00
		TOTAL			33	33	100.00