SPI_HOST Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: e383c23

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	26.000s	1.917ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	2.000s	21.194us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	110.053us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	160.300us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	34.444us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	54.733us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	110.053us	1	1	100.00
		spi_host_csr_aliasing	2.000s	34.444us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	20.520us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	36.336us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	3.000s	38.754us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	220.745us	1	1	100.00
		spi_host_error_cmd	1.000s	94.046us	1	1	100.00
		spi_host_event	23.000s	1.696ms	1	1	100.00
V2	clock_rate	spi_host_speed	6.000s	119.940us	1	1	100.00
V2	speed	spi_host_speed	6.000s	119.940us	1	1	100.00
V2	chip_select_timing	spi_host_speed	6.000s	119.940us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	11.000s	364.148us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	62.414us	1	1	100.00
V2	cpol_cpha	spi_host_speed	6.000s	119.940us	1	1	100.00
V2	full_cycle	spi_host_speed	6.000s	119.940us	1	1	100.00
V2	duplex	spi_host_smoke	26.000s	1.917ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	26.000s	1.917ms	1	1	100.00
V2	stress_all	spi_host_stress_all	14.000s	1.793ms	1	1	100.00
V2	spien	spi_host_spien	2.000s	759.446us	1	1	100.00
V2	stall	spi_host_status_stall	37.000s	3.440ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	7.000s	771.772us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	220.745us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	39.155us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	21.448us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	144.998us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	144.998us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	2.000s	21.194us	1	1	100.00
		spi_host_csr_rw	1.000s	110.053us	1	1	100.00
		spi_host_csr_aliasing	2.000s	34.444us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	51.974us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	2.000s	21.194us	1	1	100.00
		spi_host_csr_rw	1.000s	110.053us	1	1	100.00
		spi_host_csr_aliasing	2.000s	34.444us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	51.974us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	2.000s	116.723us	1	1	100.00
		spi_host_sec_cm	1.000s	86.572us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	2.000s	116.723us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.000s	121.322us	1	1	100.00
		TOTAL			26	26	100.00