SRAM_CTRL/MAIN Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: e383c23

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	18.650s	516.139us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.800s	60.292us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.840s	24.254us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.580s	95.973us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.750s	17.649us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.250s	395.721us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.840s	24.254us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	17.649us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	2.037m	10.147ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.033m	5.457ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.611m	8.120ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.961m	5.486ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	33.141m	556.885ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.829m	13.793ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	37.550s	13.959ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.241m	17.038ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	4.730s	2.211ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.222m	41.544ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	35.250s	5.683ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	27.750s	3.154ms	1	1	100.00
		sram_ctrl_throughput_w_readback	59.710s	1.851ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.121m	9.633ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.320s	822.505us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	1.985h	265.831ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.000s	23.249us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.390s	318.008us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.390s	318.008us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.800s	60.292us	1	1	100.00
		sram_ctrl_csr_rw	0.840s	24.254us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	17.649us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.080s	77.260us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.800s	60.292us	1	1	100.00
		sram_ctrl_csr_rw	0.840s	24.254us	1	1	100.00
		sram_ctrl_csr_aliasing	0.750s	17.649us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.080s	77.260us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	15.660s	7.541ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.930s	14.490us	0	1	0.00
		sram_ctrl_tl_intg_err	1.790s	224.205us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.930s	14.490us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.790s	224.205us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.121m	9.633ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.121m	9.633ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.840s	24.254us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.241m	17.038ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.241m	17.038ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.241m	17.038ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	37.550s	13.959ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.460s	2.790ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	15.660s	7.541ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	6.330s	665.098us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	18.650s	516.139us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	18.650s	516.139us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.241m	17.038ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.930s	14.490us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	37.550s	13.959ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.930s	14.490us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.930s	14.490us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	18.650s	516.139us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.930s	14.490us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	9.540s	1.085ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.115275947518938330198795030959438358621167783094150348756046637223222190865731
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 665098244 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x57) != exp (0x67)
        UVM_INFO @ 665098244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.73320587720147004496326252010806572125564208396722758211076056419922138308386
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @  14490050 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @  14490050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---