SRAM_CTRL/RET Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: e383c23

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	8.440s	218.075us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.670s	33.181us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.680s	99.452us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.140s	1.956ms	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.710s	62.642us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.840s	31.176us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.680s	99.452us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	62.642us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.760s	95.081us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.550s	773.973us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	5.599m	4.294ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	4.349m	15.208ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	37.100s	2.480ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.818m	1.947ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	4.810s	1.775ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.633m	14.508ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.480s	3.987ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.396m	98.364ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	36.710s	246.036us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	18.780s	112.381us	1	1	100.00
		sram_ctrl_throughput_w_readback	21.900s	1.075ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	16.730s	2.728ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.740s	382.406us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	20.770m	34.303ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.660s	119.808us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.980s	113.010us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.980s	113.010us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.670s	33.181us	1	1	100.00
		sram_ctrl_csr_rw	0.680s	99.452us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	62.642us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.730s	71.754us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.670s	33.181us	1	1	100.00
		sram_ctrl_csr_rw	0.680s	99.452us	1	1	100.00
		sram_ctrl_csr_aliasing	0.710s	62.642us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.730s	71.754us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.300s	423.978us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.690s	9.215us	0	1	0.00
		sram_ctrl_tl_intg_err	1.630s	914.094us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.690s	9.215us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.630s	914.094us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	16.730s	2.728ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	16.730s	2.728ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.680s	99.452us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.633m	14.508ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.633m	14.508ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.633m	14.508ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	4.810s	1.775ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.860s	75.222us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.300s	423.978us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.810s	54.340us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	8.440s	218.075us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	8.440s	218.075us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.633m	14.508ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.690s	9.215us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	4.810s	1.775ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.690s	9.215us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.690s	9.215us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	8.440s	218.075us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.690s	9.215us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	47.320s	900.852us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.113208158565570692768425292773619024118029762904022225873378077448630055744037
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   9215415 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   9215415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---