SYSRST_CTRL Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: e383c23

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	1.730s	2.128ms	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	5.930s	2.459ms	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	4.900s	2.435ms	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	5.350s	2.515ms	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	6.230s	6.020ms	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	1.750s	2.116ms	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	16.960s	26.015ms	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	6.410s	2.580ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	1.250s	2.279ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	1.750s	2.116ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.410s	2.580ms	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	3.599m	127.432ms	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	11.960s	20.348ms	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	2.170s	3.562ms	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	4.880s	3.359ms	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	2.730s	2.517ms	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	2.620s	2.120ms	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	22.445m	719.044ms	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	1.640s	2.617ms	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.530s	9.100ms	0	1	0.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	16.910s	36.301ms	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	6.140s	6.584ms	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	2.470s	2.016ms	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	1.490s	2.046ms	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	3.970s	2.298ms	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	3.970s	2.298ms	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	6.230s	6.020ms	1	1	100.00
		sysrst_ctrl_csr_rw	1.750s	2.116ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.410s	2.580ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	1.770s	5.314ms	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	6.230s	6.020ms	1	1	100.00
		sysrst_ctrl_csr_rw	1.750s	2.116ms	1	1	100.00
		sysrst_ctrl_csr_aliasing	6.410s	2.580ms	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	1.770s	5.314ms	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	sysrst_ctrl_sec_cm	41.400s	42.042ms	1	1	100.00
		sysrst_ctrl_tl_intg_err	10.050s	22.287ms	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	10.050s	22.287ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	6.210s	11.569ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 1 failures:
  • Test sysrst_ctrl_ultra_low_pwr has 1 failures.

    • 0.sysrst_ctrl_ultra_low_pwr.99221024764521045782870764447604534228811711173084035379129064937152825746939
      Line 381, in log /nightly/current_run/scratch/master/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest/run.log

        UVM_ERROR @ 2475314936 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
        UVM_INFO @ 2572814936 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
        UVM_INFO @ 3882814936 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
        UVM_INFO @ 8302814936 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
        UVM_INFO @ 9072814936 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check