UART Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: e383c23

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.320s	704.773us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.800s	14.531us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.710s	17.544us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.220s	713.818us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.640s	47.605us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.950s	24.179us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.710s	17.544us	1	1	100.00
		uart_csr_aliasing	0.640s	47.605us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	19.660s	111.636ms	1	1	100.00
V2	parity	uart_smoke	1.320s	704.773us	1	1	100.00
		uart_tx_rx	19.660s	111.636ms	1	1	100.00
V2	parity_error	uart_intr	41.460s	74.523ms	1	1	100.00
		uart_rx_parity_err	34.280s	56.397ms	1	1	100.00
V2	watermark	uart_tx_rx	19.660s	111.636ms	1	1	100.00
		uart_intr	41.460s	74.523ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.530m	181.229ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	39.370s	33.876ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	12.040s	91.443ms	1	1	100.00
V2	rx_frame_err	uart_intr	41.460s	74.523ms	1	1	100.00
V2	rx_break_err	uart_intr	41.460s	74.523ms	1	1	100.00
V2	rx_timeout	uart_intr	41.460s	74.523ms	1	1	100.00
V2	perf	uart_perf	2.969m	11.570ms	1	1	100.00
V2	sys_loopback	uart_loopback	11.430s	9.760ms	1	1	100.00
V2	line_loopback	uart_loopback	11.430s	9.760ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	11.930s	53.055ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.270s	1.523ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	5.100s	7.495ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	20.540s	5.788ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.501m	80.801ms	1	1	100.00
V2	stress_all	uart_stress_all	49.980s	77.919ms	0	1	0.00
V2	alert_test	uart_alert_test	0.800s	20.090us	1	1	100.00
V2	intr_test	uart_intr_test	0.570s	11.457us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.020s	83.089us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.020s	83.089us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.800s	14.531us	1	1	100.00
		uart_csr_rw	0.710s	17.544us	1	1	100.00
		uart_csr_aliasing	0.640s	47.605us	1	1	100.00
		uart_same_csr_outstanding	0.730s	21.860us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.800s	14.531us	1	1	100.00
		uart_csr_rw	0.710s	17.544us	1	1	100.00
		uart_csr_aliasing	0.640s	47.605us	1	1	100.00
		uart_same_csr_outstanding	0.730s	21.860us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.010s	47.849us	1	1	100.00
		uart_tl_intg_err	0.980s	152.597us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.980s	152.597us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	5.660s	564.195us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.89603698241536977348432418276593915584836473031538488664977302982725160152314
      Line 113, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 71889901490 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 71889901490 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 73632181490 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 73632181490 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 74678681490 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1