CHIP Simulation Results

Monday October 27 2025 19:18:22 UTC

GitHub Revision: `e383c23`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	2.736m	3.178ms	1	1	100.00
		chip_sw_example_rom	1.438m	3.013ms	1	1	100.00
		chip_sw_example_manufacturer	1.695m	2.593ms	1	1	100.00
		chip_sw_example_concurrency	2.675m	2.685ms	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	2.287m	4.706ms	1	1	100.00
V1	csr_rw	chip_csr_rw	3.722m	4.487ms	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	10.324m	8.534ms	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	53.793m	28.101ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	41.350s	1.995ms	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	53.793m	28.101ms	1	1	100.00
		chip_csr_rw	3.722m	4.487ms	1	1	100.00
V1	xbar_smoke	xbar_smoke	5.460s	48.972us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	4.865m	3.806ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	4.865m	3.806ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	4.865m	3.806ms	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	5.784m	4.320ms	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	5.784m	4.320ms	1	1	100.00
		chip_sw_uart_tx_rx_idx1	6.572m	4.436ms	1	1	100.00
		chip_sw_uart_tx_rx_idx2	6.252m	4.308ms	1	1	100.00
		chip_sw_uart_tx_rx_idx3	6.477m	4.506ms	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	16.585m	7.540ms	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	18.380m	8.628ms	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	4.064m	3.995ms	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	3.125m	4.909ms	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.125m	4.909ms	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	2.844m	3.566ms	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	3.197m	3.164ms	0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.224m	3.516ms	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	11.551m	11.766ms	1	1	100.00
		chip_tap_straps_testunlock0	4.003m	4.657ms	1	1	100.00
		chip_tap_straps_rma	1.393m	2.454ms	1	1	100.00
		chip_tap_straps_prod	11.338m	11.024ms	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	2.136m	3.354ms	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	13.054m	9.360ms	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	5.370m	4.747ms	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	5.370m	4.747ms	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.229m	7.904ms	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	20.429m	15.613ms	1	1	100.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.479m	3.946ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.302m	5.829ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.112m	18.920ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.611m	2.545ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.549m	6.434ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.783m	3.456ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.572m	9.408ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.104m	2.997ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.048m	3.347ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.192m	3.148ms	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	3.646m	3.620ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	8.863m	9.158ms	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.602m	5.111ms	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.962m	2.708ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	3.602m	5.111ms	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	2.071m	2.916ms	1	1	100.00
		chip_sw_aes_smoketest	2.001m	3.244ms	1	1	100.00
		chip_sw_aon_timer_smoketest	2.519m	2.806ms	1	1	100.00
		chip_sw_clkmgr_smoketest	1.871m	2.805ms	1	1	100.00
		chip_sw_csrng_smoketest	1.948m	2.053ms	1	1	100.00
		chip_sw_entropy_src_smoketest	10.396m	5.677ms	1	1	100.00
		chip_sw_gpio_smoketest	2.114m	2.244ms	1	1	100.00
		chip_sw_hmac_smoketest	3.157m	3.019ms	1	1	100.00
		chip_sw_kmac_smoketest	2.720m	2.668ms	1	1	100.00
		chip_sw_otbn_smoketest	20.883m	10.145ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.051m	6.674ms	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	4.663m	5.292ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.644m	2.705ms	1	1	100.00
		chip_sw_rv_timer_smoketest	2.296m	3.300ms	1	1	100.00
		chip_sw_rstmgr_smoketest	1.929m	2.127ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	1.724m	2.562ms	1	1	100.00
		chip_sw_uart_smoketest	3.255m	3.223ms	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	2.862m	2.407ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	4.561m	3.598ms	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.230h	61.838ms	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	40.944m	14.967ms	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.959m	16.066ms	0	1	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	3.356m	2.829ms	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	2.885m	3.636ms	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.985h	52.748ms	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.051h	55.831ms	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.781m	3.257ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.781m	3.257ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	53.793m	28.101ms	1	1	100.00
		chip_same_csr_outstanding	18.766m	15.241ms	1	1	100.00
		chip_csr_hw_reset	2.287m	4.706ms	1	1	100.00
		chip_csr_rw	3.722m	4.487ms	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	53.793m	28.101ms	1	1	100.00
		chip_same_csr_outstanding	18.766m	15.241ms	1	1	100.00
		chip_csr_hw_reset	2.287m	4.706ms	1	1	100.00
		chip_csr_rw	3.722m	4.487ms	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	29.950s	524.005us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.740s	40.955us	1	1	100.00
		xbar_smoke_large_delays	51.680s	8.582ms	1	1	100.00
		xbar_smoke_slow_rsp	36.120s	3.956ms	1	1	100.00
		xbar_random_zero_delays	12.600s	203.055us	1	1	100.00
		xbar_random_large_delays	2.675m	25.117ms	1	1	100.00
		xbar_random_slow_rsp	3.319m	23.230ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	6.290s	147.621us	1	1	100.00
		xbar_error_and_unmapped_addr	30.550s	1.283ms	1	1	100.00
V2	xbar_error_cases	xbar_error_random	18.850s	335.336us	1	1	100.00
		xbar_error_and_unmapped_addr	30.550s	1.283ms	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.488m	3.993ms	1	1	100.00
		xbar_access_same_device_slow_rsp	10.284m	69.045ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	16.230s	274.595us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	3.179m	4.206ms	1	1	100.00
		xbar_stress_all_with_error	42.090s	871.728us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	1.992m	350.690us	1	1	100.00
		xbar_stress_all_with_reset_error	35.300s	88.232us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.944m	14.967ms	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	37.478m	26.878ms	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	43.745m	14.785ms	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	34.183m	11.318ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	45.212m	16.797ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	44.237m	15.558ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	41.997m	15.417ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.934m	15.049ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	25.940s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	22.220s	10.380us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	17.370s	10.360us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	16.300s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	18.210s	10.220us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	16.820s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	17.670s	10.240us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	22.250s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.690s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	17.350s	10.200us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	16.990s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	18.930s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.040s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.840s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	19.610s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	20.640s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	16.780s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	22.170s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	18.720s	10.320us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	18.220s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.890s	10.160us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.450s	10.340us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.840s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	17.490s	10.220us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	17.020s	10.360us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	33.500m	11.229ms	1	1	100.00
		rom_e2e_asm_init_dev	41.885m	15.438ms	1	1	100.00
		rom_e2e_asm_init_prod	43.077m	15.591ms	1	1	100.00
		rom_e2e_asm_init_prod_end	40.783m	16.559ms	1	1	100.00
		rom_e2e_asm_init_rma	40.511m	14.573ms	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	38.892m	15.390ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	39.198m	15.044ms	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	40.618m	15.578ms	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.287m	16.125ms	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.780m	34.536ms	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.780m	34.536ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.178m	3.252ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.611m	2.545ms	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	2.620m	3.044ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	2.551m	2.517ms	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	16.494m	8.559ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	2.615m	2.856ms	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	3.998m	4.232ms	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	7.153m	4.808ms	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	9.420m	5.267ms	1	1	100.00
		chip_plic_all_irqs_10	4.237m	3.815ms	1	1	100.00
		chip_plic_all_irqs_20	6.960m	4.649ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	3.436m	3.627ms	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	16.396m	10.966ms	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	4.109m	4.290ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	2.148m	2.503ms	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings			0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.485m	6.704ms	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	15.344m	7.801ms	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	13.094m	7.783ms	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	2.031h	254.849ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	3.590m	3.816ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	4.051m	6.674ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	3.590m	3.816ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.782m	6.931ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	6.782m	6.931ms	1	1	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	3.698m	6.254ms	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	6.271m	4.830ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	9.409m	5.750ms	1	1	100.00
		chip_sw_aes_idle	2.551m	2.517ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.556m	3.567ms	1	1	100.00
		chip_sw_kmac_idle	2.605m	2.320ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	3.756m	4.026ms	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	4.500m	3.716ms	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	3.254m	4.590ms	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	3.525m	4.036ms	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	11.815m	11.403ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.499m	3.993ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.936m	3.952ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.582m	3.525ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.988m	5.003ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.214m	3.319ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.257m	5.081ms	1	1	100.00
		chip_sw_ast_clk_outputs	10.229m	7.904ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	7.632m	9.575ms	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.582m	3.525ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.988m	5.003ms	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	6.479m	3.946ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.302m	5.829ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.112m	18.920ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	2.611m	2.545ms	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	9.549m	6.434ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.783m	3.456ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.572m	9.408ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.104m	2.997ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.048m	3.347ms	1	1	100.00
		chip_sw_clkmgr_jitter	2.192m	3.148ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	2.148m	2.636ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	6.320m	5.159ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	11.038m	6.342ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	52.325m	24.660ms	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	2.355m	3.056ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	2.809m	3.296ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	18.208m	11.870ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	2.281m	2.760ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	5.298m	5.068ms	1	1	100.00
		chip_sw_flash_init_reduced_freq	19.151m	18.446ms	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	3.130h	135.592ms	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.229m	7.904ms	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	5.912m	4.250ms	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	3.619m	3.638ms	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	7.153m	4.808ms	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	14.485m	6.704ms	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	10.963m	6.070ms	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	2.776m	3.040ms	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	6.552m	6.521ms	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	2.315m	2.603ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.219h	25.780ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	2.022m	2.318ms	1	1	100.00
		chip_sw_edn_entropy_reqs	8.292m	5.932ms	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	2.022m	2.318ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	10.963m	6.070ms	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.754m	2.249ms	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	17.937m	16.318ms	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	8.875m	5.609ms	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	9.302m	5.829ms	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	5.486m	4.188ms	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	6.479m	3.946ms	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	58.655m	43.737ms	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	17.937m	16.318ms	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	3.571m	3.836ms	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	15.044m	8.936ms	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.741m	4.609ms	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	58.655m	43.737ms	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	4.741m	4.609ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.741m	4.609ms	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	4.741m	4.609ms	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	4.741m	4.609ms	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	7.153m	4.808ms	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	5.716m	14.103ms	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	9.719m	5.427ms	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	6.593m	4.883ms	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	6.593m	4.883ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.224m	2.710ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	2.783m	3.456ms	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.556m	3.567ms	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	2.164m	2.656ms	0	1	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	5.567m	3.675ms	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	6.712m	5.124ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	6.412m	4.248ms	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	7.309m	5.119ms	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	3.449m	3.326ms	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	15.044m	8.936ms	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	17.572m	9.408ms	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	23.221m	10.246ms	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	16.494m	8.559ms	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	44.441m	14.228ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	2.349m	2.455ms	1	1	100.00
		chip_sw_kmac_mode_kmac	2.224m	3.321ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	3.104m	2.997ms	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	15.044m	8.936ms	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.958m	5.433ms	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	2.246m	2.742ms	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	17.011m	7.706ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	2.605m	2.320ms	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	3.998m	4.232ms	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	11.551m	11.766ms	1	1	100.00
		chip_tap_straps_rma	1.393m	2.454ms	1	1	100.00
		chip_tap_straps_prod	11.338m	11.024ms	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.442m	2.764ms	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.958m	5.433ms	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.958m	5.433ms	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.958m	5.433ms	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	25.913m	12.192ms	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	4.741m	4.609ms	1	1	100.00
		chip_sw_flash_rma_unlocked	58.655m	43.737ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.127m	3.141ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.092m	5.702ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.598m	6.601ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.787m	5.956ms	0	1	0.00
		chip_sw_lc_ctrl_transition	3.958m	5.433ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.044m	8.936ms	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	4.071m	9.523ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	9.269m	9.720ms	1	1	100.00
		chip_prim_tl_access	5.716m	14.103ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	7.632m	9.575ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	6.499m	3.993ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	5.936m	3.952ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	5.582m	3.525ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	5.988m	5.003ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	5.214m	3.319ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	6.257m	5.081ms	1	1	100.00
		chip_tap_straps_dev	11.551m	11.766ms	1	1	100.00
		chip_tap_straps_rma	1.393m	2.454ms	1	1	100.00
		chip_tap_straps_prod	11.338m	11.024ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.180m	4.213ms	0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.513m	3.784ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.709m	3.492ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.363m	3.639ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	1.299m	2.920ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	20.170m	21.991ms	1	1	100.00
		chip_rv_dm_lc_disabled	1.180m	4.213ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.052h	49.790ms	1	1	100.00
		chip_sw_lc_walkthrough_prod	1.137h	49.741ms	1	1	100.00
		chip_sw_lc_walkthrough_prodend	10.723m	9.022ms	1	1	100.00
		chip_sw_lc_walkthrough_rma	1.158h	49.712ms	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	20.170m	21.991ms	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	59.880s	2.744ms	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.108m	2.938ms	1	1	100.00
		rom_volatile_raw_unlock	1.174m	2.461ms	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	56.720m	17.847ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	56.112m	18.920ms	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	9.409m	5.750ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	9.409m	5.750ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	9.409m	5.750ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	5.037m	3.448ms	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.958m	5.433ms	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	17.937m	16.318ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.037m	3.448ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.044m	8.936ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.118m	4.808ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.128m	3.042ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	17.937m	16.318ms	1	1	100.00
		chip_sw_otbn_mem_scramble	5.037m	3.448ms	1	1	100.00
		chip_sw_keymgr_key_derivation	15.044m	8.936ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	6.118m	4.808ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.128m	3.042ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.958m	5.433ms	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	5.676m	4.648ms	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	2.442m	2.764ms	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	3.127m	3.141ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	7.092m	5.702ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	6.598m	6.601ms	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	6.787m	5.956ms	0	1	0.00
		chip_sw_lc_ctrl_transition	3.958m	5.433ms	1	1	100.00
		chip_prim_tl_access	5.716m	14.103ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	5.716m	14.103ms	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	16.579m	9.041ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	5.074m	8.702ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	17.529m	23.562ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	4.477m	7.676ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	6.263m	6.816ms	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	5.582m	5.495ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	15.193m	22.258ms	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	11.732m	12.780ms	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	6.782m	6.931ms	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	13.020m	12.844ms	1	1	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	5.109m	4.122ms	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	5.074m	8.702ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	4.617m	4.882ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	13.511m	12.783ms	0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	5.275m	6.169ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	5.503m	5.263ms	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.178m	24.041ms	1	1	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.177m	7.573ms	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	12.570m	9.688ms	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	22.470m	23.172ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	3.301m	3.413ms	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	7.153m	4.808ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	4.071m	9.523ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	4.071m	9.523ms	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	12.570m	9.688ms	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	26.178m	24.041ms	1	1	100.00
		chip_sw_pwrmgr_wdog_reset	5.109m	4.122ms	1	1	100.00
		chip_sw_pwrmgr_smoketest	4.051m	6.674ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.436m	4.364ms	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	4.453m	4.211ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	4.984m	4.152ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	16.396m	10.966ms	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	2.445m	3.178ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	7.153m	4.808ms	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	15.344m	7.801ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.864m	4.381ms	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	7.803m	4.984ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.289m	3.404ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.128m	3.042ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	4.453m	4.211ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	4.453m	4.211ms	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	25.299m	18.385ms	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	15.495m	13.544ms	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.436m	4.364ms	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	5.641m	4.546ms	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	4.589m	6.955ms	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	1.393m	2.454ms	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	1.180m	4.213ms	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	9.420m	5.267ms	1	1	100.00
		chip_plic_all_irqs_10	4.237m	3.815ms	1	1	100.00
		chip_plic_all_irqs_20	6.960m	4.649ms	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.705m	2.465ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	2.272m	2.927ms	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.944m	14.967ms	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	7.273m	6.647ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.341m	3.313ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	2.742m	3.400ms	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	2.875m	3.198ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	6.118m	4.808ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	4.048m	3.347ms	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	5.007m	6.730ms	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	8.490m	8.752ms	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	9.269m	9.720ms	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	7.153m	4.808ms	1	1	100.00
		chip_sw_data_integrity_escalation	5.370m	4.747ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	10.177m	7.573ms	1	1	100.00
		chip_sw_sysrst_ctrl_reset	14.921m	22.919ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	2.763m	3.058ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	3.258m	3.498ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	5.159m	3.855ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	14.921m	22.919ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	14.921m	22.919ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	41.597m	20.300ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	41.597m	20.300ms	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	3.685m	4.865ms	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	54.780m	34.536ms	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.321m	2.629ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	1.684m	2.446ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	5.610m	3.126ms	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	4.814m	3.520ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	18.914m	8.082ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.399h	31.733ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	31.760m	11.580ms	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	2.737m	2.973ms	1	1	100.00
V2		TOTAL			233	275	84.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	2.554m	2.888ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.809m	3.156ms	0	1	0.00
V2S		TOTAL			1	2	50.00
V3	chip_sw_coremark	chip_sw_coremark	2.555h	71.820ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	8.134m	3.989ms	0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	17.880m	11.518ms	1	1	100.00
		rom_e2e_jtag_debug_dev	19.681m	12.397ms	1	1	100.00
		rom_e2e_jtag_debug_rma	3.264m	4.215ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	3.389m	3.771ms	1	1	100.00
		rom_e2e_jtag_inject_dev	3.412m	3.293ms	1	1	100.00
		rom_e2e_jtag_inject_rma	3.177m	5.231ms	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.272s		0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	8.343m	5.339ms	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	5.326m	3.046ms	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	19.671m	7.405ms	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	24.352m	9.895ms	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	3.614m	2.029ms	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	9.728m	5.512ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	1.394m	2.757ms	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	2.992m	3.522ms	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	5.146m	6.143ms	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	4.704m	5.126ms	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	12.570m	9.688ms	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	17.880m	11.518ms	1	1	100.00
		rom_e2e_jtag_debug_dev	19.681m	12.397ms	1	1	100.00
		rom_e2e_jtag_debug_rma	3.264m	4.215ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	6.387m	5.543ms	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	7.153m	4.808ms	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	1.576h	37.711ms	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	1.576h	37.711ms	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	2.489m	2.896ms	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	5.784m	4.320ms	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	52.192m	19.152ms	1	1	100.00
V3		TOTAL			19	23	82.61
	Unmapped tests	chip_sival_flash_info_access	2.774m	2.753ms	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	6.445m	5.404ms	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	40.728m	34.415ms	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	2.465m	2.569ms	1	1	100.00
		chip_sw_otp_ctrl_descrambling	2.880m	3.399ms	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	4.048m	3.779ms	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	11.292s		0	1	0.00
		chip_sw_flash_ctrl_write_clear	2.780m	3.469ms	1	1	100.00
		TOTAL			276	326	84.66

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.76658692795328662725279311337937846897920400184811510969921399675108966099852
    Line 485, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.115238117560154555411912582160052535695136557672897129181211740395419763671492
    Line 534, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.70859507398506352098883397767194985048054161876944277874470899589302045516684
    Line 509, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.32119569301509351961566485445337108334881900326592448199341978660981497867131
    Line 534, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.73509935926932480873107188524400624483394874408257422874907080481386897249736
    Line 532, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.68219251238163844309147606598554717011791796851765801227634472890040085964039
    Line 507, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.110299654797136177874020795389640994470019514529176695513563684998419034886406
    Line 512, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.65423763468524474796191658981765903271059997696468017885015845446692977661360
    Line 517, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1389447597170909981470329787184881290209078131102391617004977590775553692837
    Line 518, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.72631920470932185693434298569199044321320403571063452490174028499366894084206
    Line 507, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.53680504778925720195320124384029238114037954867118346512816934130686696574196
    Line 506, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.109843035279787212585611751759356303909725617415570530676889877270935377295428
    Line 538, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.114195714755121882297755432011124372897987489083088921165451955092077396757802
    Line 520, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.112842008454974258146126650944983860311751160317245626721165521924766187167830
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3522.155502 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3522.155502 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.57235624677124007119328513437180780903935638875027664711807459948539242413670
    Line 393, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3040.355404 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3040.355404 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 2 failures:
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.78306483476063859166183188810983954922123943551203164449466407964765988596890
    Line 406, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 6816.425000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 6816.425000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_random_sleep_power_glitch_reset has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.22801157639058832939574976332992142740460584467890541617636870326106763471862
    Line 435, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 12783.316000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 12783.316000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.47804661035214952603565357644537135135848419715123709348466720243362673982659
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.175s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.36026082510698731107975810339525801580567839656718066031427623542176118510685
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.176s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.62567319254979124338436573468068862534761928917742512381459383380460038020989
    Line 552, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.109766233496928598640857744231326563362878299700633021239214746926385670381337
    Line 476, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.76533733651647576760721175226850197422050833516347968165218270930199249899554
    Line 512, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.99892712858998079578315983261281041471033115787607136625979073973545207477649
    Line 494, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(pin_wkup_req_o))' has 1 failures:
- Test chip_sw_sleep_pin_wake has 1 failures.
  - 0.chip_sw_sleep_pin_wake.56300892416455469068549595523980213196095795173634694130471770355469400032165
    Line 469, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log
```
      Offending '(!$isunknown(pin_wkup_req_o))'
  UVM_ERROR @ 3163.768000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
  UVM_INFO @ 3163.768000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.111357790839471880655840360802459865716290677695758663288714520027045684517341
    Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3313.196870 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3313.196870 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.81650340027393318382435758496981091055747835817796840337249955915148235595070
    Line 432, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 5955.764001 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 5955.764001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.4178622572606720199141922428918260421293964407068934759095972164723898974244
    Line 441, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 34414.675575 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 34414.675575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@111570) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.23356092665016990829319792086988955816666821476329097795330147556573863934814
Line 409, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4210.867460 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@111570) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h0  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h0  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4210.867460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.75299368605615703242686591010926676285401721754946449084869732223610628116452
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34536.344695 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34536.344695 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:337)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.107284884915994892510344543498586010054206019867144237918584814224760472892162
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2855.885336 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:337)] CHECK-fail: Expect alert 25!
  UVM_INFO @ 2855.885336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.66471259362568634736257836961193455511752410615902900586119884153711359678329
    Line 391, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2502.653048 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2502.653048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.15921897290788883068769111922848397707340886049754684769355614665198014701179
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: *. has 1 failures:
- Test chip_sw_hmac_oneshot has 1 failures.
  - 0.chip_sw_hmac_oneshot.82793715030798036778382835197707132083582567853143529490998752415567568945721
    Line 394, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_hmac_oneshot/latest/run.log
```
  UVM_ERROR @ 2655.566189 us: (sw_logger_if.sv:526) [hmac_functest_sim_dv(sw/device/tests/crypto/hmac_functest.c:79)] Finished test run_test_vector: 8000534a.
  UVM_INFO @ 2655.566189 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@146382) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.71172983047388654574546085432772710597504075096063796377685158897962644653155
Line 215, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3256.682832 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@146382) { a_addr: 'h10530  a_data: 'hfce4ca2e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h23  a_opcode: 'h4  a_user: 'h1aeeb  d_param: 'h0  d_source: 'h23  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3256.682832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.66902701196829730604198909123966433202402452533007133264635526131294698142922
    Line 208, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 4212.756064 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x1061c read out mismatch
  UVM_INFO @ 4212.756064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 1 failures:
- Test chip_sw_rv_core_ibex_lockstep_glitch has 1 failures.
  - 0.chip_sw_rv_core_ibex_lockstep_glitch.111035786078075222507022105461730862513086945902006847907449069333063160906358
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
```
  UVM_FATAL @ 3155.562310 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
  UVM_INFO @ 3155.562310 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.20099491406731552449740962384123405066441535526866174186038210085556602686433
    Line 395, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 2828.994500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2828.994500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.29396984223018783512111296955958476443084864599498819146080399830822702189861
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 3635.827000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3635.827000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:196) [chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= * (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.90556311141415397802625108244429423027341501432450221554693275518034881037967
    Line 444, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3988.707069 us: (chip_sw_power_virus_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed csrng_acmd_q >= 2 (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 3988.707069 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.12190616417985180382370341122984494387287270827665138269066376339126661287479
    Line 478, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.45661816164418774206190103792021286204009800074024833172515554558827419435871
    Line 498, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.47725049206655670433854935474425378692551355230264640974463462782710409096993
    Line 444, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_ERROR @ 4215.096059 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 4215.096059 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_sw_lc_raw_unlock_vseq.sv:57) [chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement has 1 failures:
- Test rom_raw_unlock has 1 failures.
  - 0.rom_raw_unlock.4484956167273180964963329882125189358693295154253563508709065295100834235503
    Line 422, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_raw_unlock/latest/run.log
```
  UVM_FATAL @ 16065.699543 us: (chip_sw_lc_raw_unlock_vseq.sv:57) [uvm_test_top.env.virtual_sequencer.chip_sw_lc_raw_unlock_vseq] Timed out waiting for clkmgr to confirm extclk enablement
  UVM_INFO @ 16065.699543 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33066) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.31063028992415385800592186660187029604828763949624159139014718119600991762528
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1994.506648 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33066) { a_addr: 'h107ac  a_data: 'hb6741bd5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h27  a_opcode: 'h4  a_user: 'h1a993  d_param: 'h0  d_source: 'h27  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1994.506648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---