ADC_CTRL Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	5.440s	5.753ms	1	1	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	1.070s	985.195us	1	1	100.00
V1	csr_rw	adc_ctrl_csr_rw	0.750s	374.453us	1	1	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	35.090s	49.212ms	1	1	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	3.060s	834.345us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	1.800s	527.621us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	0.750s	374.453us	1	1	100.00
		adc_ctrl_csr_aliasing	3.060s	834.345us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	filters_polled	adc_ctrl_filters_polled	6.744m	488.251ms	1	1	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	9.536m	333.432ms	1	1	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	4.701m	163.084ms	1	1	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	4.128m	164.654ms	1	1	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	5.835m	221.082ms	1	1	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	2.723m	200.635ms	1	1	100.00
V2	filters_both	adc_ctrl_filters_both	7.323m	494.020ms	1	1	100.00
V2	clock_gating	adc_ctrl_clock_gating	4.712m	189.301ms	0	1	0.00
V2	poweron_counter	adc_ctrl_poweron_counter	1.140s	3.326ms	1	1	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	10.280s	36.003ms	1	1	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	35.610s	81.695ms	1	1	100.00
V2	stress_all	adc_ctrl_stress_all	2.235m	206.364ms	1	1	100.00
V2	alert_test	adc_ctrl_alert_test	1.430s	383.674us	1	1	100.00
V2	intr_test	adc_ctrl_intr_test	1.470s	475.257us	1	1	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	2.070s	822.095us	1	1	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	2.070s	822.095us	1	1	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	1.070s	985.195us	1	1	100.00
		adc_ctrl_csr_rw	0.750s	374.453us	1	1	100.00
		adc_ctrl_csr_aliasing	3.060s	834.345us	1	1	100.00
		adc_ctrl_same_csr_outstanding	14.210s	5.217ms	1	1	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	1.070s	985.195us	1	1	100.00
		adc_ctrl_csr_rw	0.750s	374.453us	1	1	100.00
		adc_ctrl_csr_aliasing	3.060s	834.345us	1	1	100.00
		adc_ctrl_same_csr_outstanding	14.210s	5.217ms	1	1	100.00
V2		TOTAL			15	16	93.75
V2S	tl_intg_err	adc_ctrl_sec_cm	5.750s	4.048ms	1	1	100.00
		adc_ctrl_tl_intg_err	3.500s	4.534ms	1	1	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	3.500s	4.534ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	17.970s	44.855ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 1 failures:
  • Test adc_ctrl_clock_gating has 1 failures.

    • 0.adc_ctrl_clock_gating.8036279776871198150406198498575945697452210019909846192382834182303098915219
      Line 165, in log /nightly/current_run/scratch/master/adc_ctrl-sim-vcs/0.adc_ctrl_clock_gating/latest/run.log

        UVM_ERROR @ 189301064009 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
        UVM_INFO @ 189301064009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---