AES/UNMASKED Simulation Results

Tuesday October 28 2025 18:45:55 UTC

GitHub Revision: 158897e

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	64.864us	1	1	100.00
V1	smoke	aes_smoke	3.000s	183.279us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.000s	70.267us	1	1	100.00
V1	csr_rw	aes_csr_rw	2.000s	58.095us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	331.615us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	2.000s	71.764us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	66.841us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	58.095us	1	1	100.00
		aes_csr_aliasing	2.000s	71.764us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	3.000s	183.279us	1	1	100.00
		aes_config_error	4.000s	354.058us	1	1	100.00
		aes_stress	3.000s	110.575us	1	1	100.00
V2	key_length	aes_smoke	3.000s	183.279us	1	1	100.00
		aes_config_error	4.000s	354.058us	1	1	100.00
		aes_stress	3.000s	110.575us	1	1	100.00
V2	back2back	aes_stress	3.000s	110.575us	1	1	100.00
		aes_b2b	2.000s	57.808us	1	1	100.00
V2	backpressure	aes_stress	3.000s	110.575us	1	1	100.00
V2	multi_message	aes_smoke	3.000s	183.279us	1	1	100.00
		aes_config_error	4.000s	354.058us	1	1	100.00
		aes_stress	3.000s	110.575us	1	1	100.00
		aes_alert_reset	2.000s	86.450us	1	1	100.00
V2	failure_test	aes_man_cfg_err	1.000s	94.379us	1	1	100.00
		aes_config_error	4.000s	354.058us	1	1	100.00
		aes_alert_reset	2.000s	86.450us	1	1	100.00
V2	trigger_clear_test	aes_clear	3.000s	191.969us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	5.000s	252.313us	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.000s	86.450us	1	1	100.00
V2	stress	aes_stress	3.000s	110.575us	1	1	100.00
V2	sideload	aes_stress	3.000s	110.575us	1	1	100.00
		aes_sideload	2.000s	76.278us	1	1	100.00
V2	deinitialization	aes_deinit	2.000s	90.491us	1	1	100.00
V2	stress_all	aes_stress_all	16.000s	1.850ms	1	1	100.00
V2	alert_test	aes_alert_test	1.000s	60.664us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.000s	376.943us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.000s	376.943us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.000s	70.267us	1	1	100.00
		aes_csr_rw	2.000s	58.095us	1	1	100.00
		aes_csr_aliasing	2.000s	71.764us	1	1	100.00
		aes_same_csr_outstanding	2.000s	110.677us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.000s	70.267us	1	1	100.00
		aes_csr_rw	2.000s	58.095us	1	1	100.00
		aes_csr_aliasing	2.000s	71.764us	1	1	100.00
		aes_same_csr_outstanding	2.000s	110.677us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	3.000s	93.198us	1	1	100.00
V2S	fault_inject	aes_fi	2.000s	91.273us	1	1	100.00
		aes_control_fi	2.000s	63.965us	1	1	100.00
		aes_cipher_fi	2.000s	84.250us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	81.646us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	81.646us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	81.646us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	81.646us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	2.000s	136.347us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	3.000s	714.219us	1	1	100.00
		aes_tl_intg_err	2.000s	130.333us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	130.333us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.000s	86.450us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	81.646us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	3.000s	183.279us	1	1	100.00
		aes_stress	3.000s	110.575us	1	1	100.00
		aes_alert_reset	2.000s	86.450us	1	1	100.00
		aes_core_fi	2.000s	92.606us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	81.646us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.000s	52.561us	1	1	100.00
		aes_stress	3.000s	110.575us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	3.000s	110.575us	1	1	100.00
		aes_sideload	2.000s	76.278us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.000s	52.561us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.000s	52.561us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.000s	52.561us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.000s	52.561us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.000s	52.561us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	3.000s	110.575us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	3.000s	110.575us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.000s	91.273us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.000s	91.273us	1	1	100.00
		aes_control_fi	2.000s	63.965us	1	1	100.00
		aes_cipher_fi	2.000s	84.250us	1	1	100.00
		aes_ctr_fi	2.000s	53.514us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.000s	91.273us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.000s	91.273us	1	1	100.00
		aes_control_fi	2.000s	63.965us	1	1	100.00
		aes_cipher_fi	2.000s	84.250us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	2.000s	84.250us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.000s	91.273us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.000s	91.273us	1	1	100.00
		aes_control_fi	2.000s	63.965us	1	1	100.00
		aes_ctr_fi	2.000s	53.514us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.000s	91.273us	1	1	100.00
		aes_control_fi	2.000s	63.965us	1	1	100.00
		aes_cipher_fi	2.000s	84.250us	1	1	100.00
		aes_ctr_fi	2.000s	53.514us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.000s	86.450us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.000s	91.273us	1	1	100.00
		aes_control_fi	2.000s	63.965us	1	1	100.00
		aes_cipher_fi	2.000s	84.250us	1	1	100.00
		aes_ctr_fi	2.000s	53.514us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.000s	91.273us	1	1	100.00
		aes_control_fi	2.000s	63.965us	1	1	100.00
		aes_cipher_fi	2.000s	84.250us	1	1	100.00
		aes_ctr_fi	2.000s	53.514us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.000s	91.273us	1	1	100.00
		aes_control_fi	2.000s	63.965us	1	1	100.00
		aes_ctr_fi	2.000s	53.514us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.000s	91.273us	1	1	100.00
		aes_control_fi	2.000s	63.965us	1	1	100.00
		aes_cipher_fi	2.000s	84.250us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.000s	160.887us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.18020658872901946061690151263379631046965642868818883940208160189526398232725
      Line 129, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 160887378 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 160887378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---